62 lines
1.7 KiB
Python
62 lines
1.7 KiB
Python
import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotbext.axi import AxiLiteBus, AxiLiteMaster
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# register indexes from axi4l_reg_map_controller_pkg.sv
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REG_CONTROL = 0
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REG_DAC_WIDTH = 2
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REG_DAC_PERIOD = 3
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REG_DAC_PULSE_NUM = 4
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REG_DAC_PULSE_HEIGHT = 5
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REG_ADC_PERIOD = 6
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REG_WINDOW_SIZE = 7
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def reg_addr(reg_index: int) -> int:
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# AXI-Lite usually uses byte addresses for 32-bit regs
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return reg_index * 4
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class TB:
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def __init__(self, dut):
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self.dut = dut
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cocotb.start_soon(Clock(dut.ctrl_clk, 10, units="ns").start())
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self.axil = AxiLiteMaster(
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AxiLiteBus.from_prefix(dut, "s_axil"),
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dut.ctrl_clk,
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dut.rst,
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)
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async def reset(self):
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self.dut.rst.value = 1
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for _ in range(5):
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await RisingEdge(self.dut.ctrl_clk)
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self.dut.rst.value = 0
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for _ in range(5):
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await RisingEdge(self.dut.ctrl_clk)
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@cocotb.test()
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async def simple_axil_write(dut):
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tb = TB(dut)
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await tb.reset()
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# Простая запись в RW-регистр REG_DAC_WIDTH.
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await tb.axil.write(reg_addr(REG_DAC_WIDTH), (0x0000_0123).to_bytes(4, "little"))
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# Не обязательно, но удобно проверить, что запись прошла через AXI-Lite.
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resp = await tb.axil.read(reg_addr(REG_DAC_WIDTH), 4)
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value = int.from_bytes(bytes(resp.data), "little")
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assert value == 0x0000_0123
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# Пример W1S-записи в control: bit 3 = cfg_bus_valid pulse.
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# Дальше уже можно проверять твою логику контроллера.
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await tb.axil.write(reg_addr(REG_CONTROL), (1 << 3).to_bytes(4, "little"))
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await RisingEdge(dut.ctrl_clk)
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