125 lines
3.1 KiB
Python
125 lines
3.1 KiB
Python
import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotbext.axi import AxiLiteBus, AxiLiteMaster
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# Register indexes from axi4l_reg_map_controller_pkg.sv
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REG_CONTROL = 0
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REG_STATUS = 1
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REG_DAC_WIDTH = 2
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REG_DAC_PERIOD = 3
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REG_DAC_PULSE_NUM = 4
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REG_DAC_PULSE_HEIGHT = 5
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REG_ADC_PERIOD = 6
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REG_WINDOW_SIZE = 7
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REG_ERROR = 8
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REG_DESC_READ_ADDR = 9
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REG_DESC_READ_LEN = 10
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REG_DESC_READ_CONFIG = 11
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REG_READ_STATUS = 12
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REG_DESC_WRITE_ADDR = 13
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REG_DESC_WRITE_LEN_AND_TAG = 14
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REG_STATUS_WRITE_LEN = 15
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REG_STATUS_WRITE_CONFIG = 16
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# REG_CONTROL pulse bits
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CTRL_START = 0
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CTRL_RST_SOFT = 1
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CTRL_CFG_BUS_VALID = 2
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CTRL_SEND_DESC_READ = 3
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CTRL_SEND_DESC_WRITE = 4
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CTRL_TAKE_STATUS_READ = 5
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CTRL_TAKE_STATUS_WRITE = 6
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def reg_addr(reg_index: int) -> int:
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# AXI-Lite uses byte addresses, 32-bit registers are spaced by 4 bytes.
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return reg_index * 4
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def u32(value: int) -> bytes:
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return int(value & 0xFFFFFFFF).to_bytes(4, "little")
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class TB:
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def __init__(self, dut):
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self.dut = dut
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cocotb.start_soon(Clock(dut.ctrl_clk, 10, units="ns").start())
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self.axil = AxiLiteMaster(
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AxiLiteBus.from_prefix(dut, "s_axil"),
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dut.ctrl_clk,
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dut.rst,
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)
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async def reset(self):
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self.dut.rst.value = 1
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for _ in range(5):
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await RisingEdge(self.dut.ctrl_clk)
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self.dut.rst.value = 0
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for _ in range(5):
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await RisingEdge(self.dut.ctrl_clk)
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async def write_reg(self, reg_index: int, value: int):
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await self.axil.write(reg_addr(reg_index), u32(value))
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async def read_reg(self, reg_index: int) -> int:
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resp = await self.axil.read(reg_addr(reg_index), 4)
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return int.from_bytes(bytes(resp.data), "little")
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@cocotb.test()
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async def simple_axil_write_read(dut):
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tb = TB(dut)
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await tb.reset()
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await tb.write_reg(REG_DAC_WIDTH, 0x0000_0123)
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value = await tb.read_reg(REG_DAC_WIDTH)
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assert value == 0x0000_0123
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@cocotb.test()
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async def simple_controller_config_write(dut):
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tb = TB(dut)
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await tb.reset()
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await tb.write_reg(REG_DAC_WIDTH, 0x10)
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await tb.write_reg(REG_DAC_PERIOD, 0x40)
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await tb.write_reg(REG_DAC_PULSE_NUM, 3)
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await tb.write_reg(REG_DAC_PULSE_HEIGHT, 0x7FF)
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await tb.write_reg(REG_ADC_PERIOD, 0x80)
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await tb.write_reg(REG_WINDOW_SIZE, 16)
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assert await tb.read_reg(REG_DAC_WIDTH) == 0x10
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assert await tb.read_reg(REG_WINDOW_SIZE) == 16
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# W1S pulse: bit 2 = cfg_bus_valid_o.
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await tb.write_reg(REG_CONTROL, 1 << CTRL_CFG_BUS_VALID)
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await RisingEdge(dut.ctrl_clk)
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@cocotb.test()
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async def simple_dma_desc_register_write(dut):
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tb = TB(dut)
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await tb.reset()
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# mock
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await tb.write_reg(REG_DESC_READ_ADDR, 0x0000_1000)
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await tb.write_reg(REG_DESC_READ_LEN, 64)
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await tb.write_reg(REG_DESC_READ_CONFIG, 0x0000_0001)
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assert await tb.read_reg(REG_DESC_READ_ADDR) == 0x0000_1000
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assert await tb.read_reg(REG_DESC_READ_LEN) == 64
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# W1S pulse: bit 3 = send_desc_read_o.
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await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_READ)
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for _ in range(3):
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await RisingEdge(dut.ctrl_clk)
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