54 lines
1.6 KiB
Systemverilog
54 lines
1.6 KiB
Systemverilog
// AN9238 virtual ADC model (1 port)
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module virtual_adc_model #(
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parameter int unsigned ADC_DATA_WIDTH = 12,
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// Bipolar input range: +/- VOLTAGE_RANGE
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parameter real VOLTAGE_RANGE = 1.0,
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// Analog input correction
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parameter real VOLTAGE_GAIN = 0.2,
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parameter real GROUND_BIAS = 0.0,
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// ADC timing parameters
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parameter time CONVERSION_DELAY = 150ps
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)(
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input logic clk_i,
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input real voltage_i,
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output logic otr_o,
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output logic [ADC_DATA_WIDTH-1:0] data_o
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);
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localparam int unsigned ZERO_CODE = (1 << (ADC_DATA_WIDTH - 1));
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localparam real VOLTAGE_STEP = VOLTAGE_RANGE / real'(ZERO_CODE);
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//------------------------------------------------------------
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// Convert analog voltage to ADC code TODO: add OTR check
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//------------------------------------------------------------
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function automatic real code_to_voltage(
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input logic [ADC_DATA_WIDTH-1:0] code
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);
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return (int'(code) - int'(ZERO_CODE)) * VOLTAGE_STEP;
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endfunction
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//------------------------------------------------------------
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// Initial state
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//------------------------------------------------------------
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initial begin
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data_o = ZERO_CODE; // 0V
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otr_o = 0;
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end
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//------------------------------------------------------------
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// Update analog output
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//------------------------------------------------------------
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always @(posedge clk_i) begin
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#(CONVERSION_DELAY);
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data_o = ;
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otr_o = ;
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end
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endmodule
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