338 lines
11 KiB
Systemverilog
338 lines
11 KiB
Systemverilog
module control #(
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parameter int unsigned DAC_DATA_WIDTH = 12
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) (
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input logic ctrl_clk,
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input logic dac_clk_in,
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input logic adc_clk_in,
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input logic rst_n,
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input logic rst_soft,
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// adc_clk_in domain
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input logic finish,
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input logic [159:0] cfg_bus_input,
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input logic cfg_bus_valid,
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input logic start,
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// status signals
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output logic busy,
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// dac_clk_in domain outputs
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output logic [31:0] dac_pulse_width,
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output logic [31:0] dac_pulse_period,
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output logic [DAC_DATA_WIDTH-1:0] dac_pulse_height,
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output logic [15:0] dac_pulse_num,
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// adc_clk_in domain outputs
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output logic [31:0] adc_pulse_period,
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output logic [15:0] adc_pulse_num,
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output logic [31:0] adc_window_size,
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// pulse outputs
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output logic dac_start,
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output logic adc_start,
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output logic dac_rst,
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output logic adc_rst
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);
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// static checks
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initial begin
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if (DAC_DATA_WIDTH > 16) begin
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$error("DAC_DATA_WIDTH must be <= 16");
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end
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if (DAC_DATA_WIDTH == 0) begin
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$error("DAC_DATA_WIDTH must be > 0");
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end
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end
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// reset synchronizers: async assert, sync deassert in each domain
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logic rst_ff1, rst_ff2;
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logic dac_rst_ff1, dac_rst_ff2;
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logic adc_rst_ff1, adc_rst_ff2;
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logic ctrl_rst;
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logic dac_rst_int;
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logic adc_rst_int;
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always_ff @(posedge ctrl_clk or negedge rst_n) begin
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if (!rst_n) begin
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rst_ff1 <= 1'b1;
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rst_ff2 <= 1'b1;
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end else begin
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rst_ff1 <= 1'b0;
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rst_ff2 <= rst_ff1;
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end
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end
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always_ff @(posedge dac_clk_in or negedge rst_n) begin
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if (!rst_n) begin
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dac_rst_ff1 <= 1'b1;
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dac_rst_ff2 <= 1'b1;
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end else begin
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dac_rst_ff1 <= 1'b0;
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dac_rst_ff2 <= dac_rst_ff1;
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end
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end
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always_ff @(posedge adc_clk_in or negedge rst_n) begin
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if (!rst_n) begin
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adc_rst_ff1 <= 1'b1;
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adc_rst_ff2 <= 1'b1;
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end else begin
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adc_rst_ff1 <= 1'b0;
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adc_rst_ff2 <= adc_rst_ff1;
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end
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end
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assign ctrl_rst = rst_ff2;
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assign dac_rst_int = dac_rst_ff2;
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assign adc_rst_int = adc_rst_ff2;
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// Pending ACKs for config delivery
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logic cfg_wait_dac_ack;
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logic cfg_wait_adc_ack;
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// Event toggles cntrl -> DAC/ADC
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logic start_toggle;
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logic rst_toggle;
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// Config request toggles cntrl -> DAC/ADC
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logic cfg_req_toggle_dac;
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logic cfg_req_toggle_adc;
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// ACK toggles DAC/ADC -> cntrl
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logic cfg_ack_toggle_dac;
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logic cfg_ack_toggle_adc;
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(* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_dac_meta, cfg_ack_toggle_dac_sync, cfg_ack_toggle_dac_sync_d;
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(* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_adc_meta, cfg_ack_toggle_adc_sync, cfg_ack_toggle_adc_sync_d;
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wire cfg_ack_pulse_dac = cfg_ack_toggle_dac_sync ^ cfg_ack_toggle_dac_sync_d;
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wire cfg_ack_pulse_adc = cfg_ack_toggle_adc_sync ^ cfg_ack_toggle_adc_sync_d;
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always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
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if (ctrl_rst) begin
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cfg_ack_toggle_dac_meta <= 1'b0;
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cfg_ack_toggle_dac_sync <= 1'b0;
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cfg_ack_toggle_dac_sync_d <= 1'b0;
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cfg_ack_toggle_adc_meta <= 1'b0;
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cfg_ack_toggle_adc_sync <= 1'b0;
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cfg_ack_toggle_adc_sync_d <= 1'b0;
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end else begin
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cfg_ack_toggle_dac_meta <= cfg_ack_toggle_dac;
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cfg_ack_toggle_dac_sync <= cfg_ack_toggle_dac_meta;
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cfg_ack_toggle_dac_sync_d <= cfg_ack_toggle_dac_sync;
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cfg_ack_toggle_adc_meta <= cfg_ack_toggle_adc;
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cfg_ack_toggle_adc_sync <= cfg_ack_toggle_adc_meta;
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cfg_ack_toggle_adc_sync_d <= cfg_ack_toggle_adc_sync;
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end
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end
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// finish event: ADC -> cntrl via toggle CDC
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logic finish_toggle_adc;
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logic finish_meta, finish_sync, finish_sync_d;
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wire finish_pulse = finish_sync ^ finish_sync_d;
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always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
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if (adc_rst_int) begin
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finish_toggle_adc <= 1'b0;
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end else if (finish) begin
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finish_toggle_adc <= ~finish_toggle_adc;
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end
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end
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always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
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if (ctrl_rst) begin
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finish_meta <= 1'b0;
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finish_sync <= 1'b0;
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finish_sync_d <= 1'b0;
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end else begin
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finish_meta <= finish_toggle_adc;
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finish_sync <= finish_meta;
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finish_sync_d <= finish_sync;
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end
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end
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logic [159:0] cfg_bus;
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always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
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if (ctrl_rst) begin
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cfg_bus <= '0;
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busy <= 0;
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start_toggle <= 0;
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rst_toggle <= 0;
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cfg_req_toggle_dac <= 0;
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cfg_req_toggle_adc <= 0;
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cfg_wait_dac_ack <= 0;
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cfg_wait_adc_ack <= 0;
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end else begin
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if (finish_pulse) begin
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busy <= 0;
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end
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if (cfg_ack_pulse_dac) begin
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cfg_wait_dac_ack <= 1'b0;
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end
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if (cfg_ack_pulse_adc) begin
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cfg_wait_adc_ack <= 1'b0;
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end
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if (cfg_bus_valid && !busy && !cfg_wait_dac_ack && !cfg_wait_adc_ack) begin
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cfg_bus <= cfg_bus_input;
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cfg_req_toggle_dac <= ~cfg_req_toggle_dac;
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cfg_req_toggle_adc <= ~cfg_req_toggle_adc;
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cfg_wait_dac_ack <= 1;
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cfg_wait_adc_ack <= 1;
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end
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if (start && !busy && !cfg_wait_dac_ack && !cfg_wait_adc_ack) begin
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start_toggle <= ~start_toggle;
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busy <= 1;
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end
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if (rst_soft) begin
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rst_toggle <= ~rst_toggle;
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end
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end
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end
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// cntrl -> DAC: start/reset event sync
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(* ASYNC_REG = "TRUE" *) logic start_meta_dac, start_sync_dac;
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logic start_sync_dac_d;
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(* ASYNC_REG = "TRUE" *) logic rst_meta_dac, rst_sync_dac;
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logic rst_sync_dac_d;
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wire dac_start_pulse = start_sync_dac ^ start_sync_dac_d;
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wire dac_rst_pulse = rst_sync_dac ^ rst_sync_dac_d;
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always_ff @(posedge dac_clk_in or posedge dac_rst_int) begin
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if (dac_rst_int) begin
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start_meta_dac <= 1'b0;
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start_sync_dac <= 1'b0;
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start_sync_dac_d <= 1'b0;
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rst_meta_dac <= 1'b0;
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rst_sync_dac <= 1'b0;
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rst_sync_dac_d <= 1'b0;
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dac_start <= 1'b0;
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dac_rst <= 1'b0;
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end else begin
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start_meta_dac <= start_toggle;
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start_sync_dac <= start_meta_dac;
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start_sync_dac_d <= start_sync_dac;
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rst_meta_dac <= rst_toggle;
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rst_sync_dac <= rst_meta_dac;
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rst_sync_dac_d <= rst_sync_dac;
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dac_start <= dac_start_pulse;
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dac_rst <= dac_rst_pulse;
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end
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end
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// cntrl -> ADC: start/reset event sync
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(* ASYNC_REG = "TRUE" *) logic start_meta_adc, start_sync_adc;
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logic start_sync_adc_d;
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(* ASYNC_REG = "TRUE" *) logic rst_meta_adc, rst_sync_adc;
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logic rst_sync_adc_d;
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wire adc_start_pulse = start_sync_adc ^ start_sync_adc_d;
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wire adc_rst_pulse = rst_sync_adc ^ rst_sync_adc_d;
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always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
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if (adc_rst_int) begin
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start_meta_adc <= 1'b0;
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start_sync_adc <= 1'b0;
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start_sync_adc_d <= 1'b0;
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rst_meta_adc <= 1'b0;
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rst_sync_adc <= 1'b0;
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rst_sync_adc_d <= 1'b0;
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adc_start <= 1'b0;
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adc_rst <= 1'b0;
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end else begin
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start_meta_adc <= start_toggle;
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start_sync_adc <= start_meta_adc;
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start_sync_adc_d <= start_sync_adc;
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rst_meta_adc <= rst_toggle;
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rst_sync_adc <= rst_meta_adc;
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rst_sync_adc_d <= rst_sync_adc;
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adc_start <= adc_start_pulse;
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adc_rst <= adc_rst_pulse;
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end
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end
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// contrl -> DAC config CDC
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// cfg_bus is kept stable in contrl domain until DAC and ADC both ACK.
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(* ASYNC_REG = "TRUE" *) logic cfg_req_meta_dac, cfg_req_sync_dac;
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logic cfg_req_sync_dac_d;
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wire cfg_req_pulse_dac = cfg_req_sync_dac ^ cfg_req_sync_dac_d;
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always_ff @(posedge dac_clk_in or posedge dac_rst_int) begin
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if (dac_rst_int) begin
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cfg_req_meta_dac <= 1'b0;
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cfg_req_sync_dac <= 1'b0;
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cfg_req_sync_dac_d<= 1'b0;
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cfg_ack_toggle_dac<= 1'b0;
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dac_pulse_width <= '0;
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dac_pulse_period <= '0;
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dac_pulse_num <= '0;
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dac_pulse_height <= '0;
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end else begin
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cfg_req_meta_dac <= cfg_req_toggle_dac;
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cfg_req_sync_dac <= cfg_req_meta_dac;
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cfg_req_sync_dac_d <= cfg_req_sync_dac;
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if (cfg_req_pulse_dac) begin
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dac_pulse_width <= cfg_bus[31:0];
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dac_pulse_period <= cfg_bus[63:32];
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dac_pulse_num <= cfg_bus[79:64];
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dac_pulse_height <= cfg_bus[80 +: DAC_DATA_WIDTH];
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cfg_ack_toggle_dac <= ~cfg_ack_toggle_dac;
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end
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end
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end
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// cntrl -> ADC config CDC
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logic cfg_req_meta_adc, cfg_req_sync_adc, cfg_req_sync_adc_d;
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wire cfg_req_pulse_adc = cfg_req_sync_adc ^ cfg_req_sync_adc_d;
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always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
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if (adc_rst_int) begin
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cfg_req_meta_adc <= 1'b0;
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cfg_req_sync_adc <= 1'b0;
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cfg_req_sync_adc_d <= 1'b0;
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cfg_ack_toggle_adc <= 1'b0;
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adc_pulse_period <= '0;
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adc_pulse_num <= '0;
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adc_window_size <= '0;
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end else begin
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cfg_req_meta_adc <= cfg_req_toggle_adc;
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cfg_req_sync_adc <= cfg_req_meta_adc;
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cfg_req_sync_adc_d <= cfg_req_sync_adc;
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if (cfg_req_pulse_adc) begin
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adc_pulse_period <= cfg_bus[127:96];
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adc_pulse_num <= cfg_bus[79:64];
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adc_window_size <= cfg_bus[159:128];
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cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc;
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end
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end
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end
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endmodule |