132 lines
3.1 KiB
Systemverilog
132 lines
3.1 KiB
Systemverilog
`timescale 1ns / 1ps
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module sampler_tb;
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parameter DATA_WIDTH = 12;
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parameter PROCESS_MODE = 0;
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parameter CLK_PERIOD = 15.3846;
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parameter TEST_NUM = 1000;
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logic clk;
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logic rst;
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logic [DATA_WIDTH-1:0] data_in;
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logic out_of_range;
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logic [DATA_WIDTH-1:0] m_axis_tdata;
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logic m_axis_tvalid;
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integer errors = 0;
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sampler #(
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.DATA_WIDTH(DATA_WIDTH),
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.PROCESS_MODE(PROCESS_MODE)
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) dut (
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.clk_in(clk),
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.rst(rst),
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.data_in(data_in),
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.out_of_range(out_of_range),
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tvalid(m_axis_tvalid)
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);
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initial begin
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clk = 0;
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forever #(CLK_PERIOD/2) clk = ~clk;
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end
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function automatic [DATA_WIDTH-1:0] ref_convert(input [DATA_WIDTH-1:0] din);
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if (PROCESS_MODE == 0)
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return din;
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else if (din == {1'b1, {(DATA_WIDTH-1){1'b0}}})
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return din;
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else
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return din[DATA_WIDTH-1] ?
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{1'b1, (~din[DATA_WIDTH-2:0] + 1'b1)} :
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din;
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endfunction
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task send(input [DATA_WIDTH-1:0] word, input bit oor);
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@(posedge clk);
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data_in <= word;
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out_of_range <= oor;
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endtask
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logic [DATA_WIDTH-1:0] exp_d0, exp_d1, exp_d2;
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logic oor_d0, oor_d1, oor_d2;
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initial begin
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$display("\n=== RANDOM SAMPLER TEST===\n");
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rst = 1;
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data_in = 0;
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out_of_range = 0;
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exp_d0 = 0;
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exp_d1 = 0;
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exp_d2 = 0;
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oor_d0 = 1;
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oor_d1 = 1;
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oor_d2 = 1;
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repeat(5) @(posedge clk);
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rst = 0;
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repeat(2) @(posedge clk);
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repeat (TEST_NUM) begin
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logic [DATA_WIDTH-1:0] rand_data;
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bit rand_oor;
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rand_data = $urandom_range(0, (1 << DATA_WIDTH) - 1);
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rand_oor = ($urandom_range(0, 99) < 20);
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@(negedge clk);
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if (!oor_d2) begin
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if (m_axis_tvalid !== 1) begin
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$display("ERROR: valid=0");
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errors++;
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end
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if (m_axis_tdata !== exp_d2) begin
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$display("ERROR: data mismatch");
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$display(" expected = %h", exp_d2);
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$display(" got = %h", m_axis_tdata);
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errors++;
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end
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end
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send(rand_data, rand_oor);
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exp_d2 = exp_d1;
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exp_d1 = exp_d0;
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exp_d0 = ref_convert(rand_data);
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oor_d2 = oor_d1;
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oor_d1 = oor_d0;
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oor_d0 = rand_oor;
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end
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@(posedge clk);
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if (!oor_d2) begin
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if (m_axis_tdata !== exp_d2) begin
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$display("ERROR: final mismatch");
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$display(" expected = %h", exp_d2);
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$display(" got = %h", m_axis_tdata);
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errors++;
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end
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end
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if (errors == 0)
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$display("\n========== ALL PASSED ==========\n");
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else
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$display("\n========== FAILED: %0d errors ==========\n", errors);
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$finish;
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end
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endmodule |