53 lines
1.4 KiB
Systemverilog
53 lines
1.4 KiB
Systemverilog
`ifndef AXIS_INTERFACE_SVH
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`define AXIS_INTERFACE_SVH
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interface axis_if #(
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parameter int DATA_WIDTH = 8
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)(
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input logic clk,
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input logic rst_n
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);
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// Сигналы шины AXI-Stream
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logic [DATA_WIDTH-1:0] tdata;
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logic tvalid;
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logic tlast;
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logic tready;
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//------------------------------------------------------------
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// Clocking block для Testbench (Driver/Monitor)
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// Защищает от Race Conditions в симуляции
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//------------------------------------------------------------
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clocking drv_cb @(posedge clk);
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default input #1step output #100ps;
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output tdata, tvalid, tlast;
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input tready;
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endclocking
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clocking mon_cb @(posedge clk);
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default input #1step;
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input tdata, tvalid, tlast, tready;
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endclocking
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//------------------------------------------------------------
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// Modports для автоматического подключения одной строчкой
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//------------------------------------------------------------
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modport master (
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output tdata, tvalid, tlast,
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input tready
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);
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modport slave (
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input tdata, tvalid, tlast,
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output tready
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);
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// Modport для тестбенча (чтобы работать через функции)
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modport tb (
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clocking drv_cb,
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clocking mon_cb
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);
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endinterface
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`endif // AXIS_INTERFACE_SVH
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