67 lines
1.2 KiB
Systemverilog
67 lines
1.2 KiB
Systemverilog
`timescale 1ns / 1ps
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module sampler_tb;
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parameter DATA_WIDTH = 12;
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parameter PACK_FACTOR = 3;
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parameter PROCESS_MODE = 0;
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parameter CLK_PERIOD = 15.3846;
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logic clk;
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logic rst;
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logic [DATA_WIDTH-1:0] data_in;
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logic out_of_range;
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logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
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logic m_axis_tvalid;
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// DUT
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sampler #(
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.DATA_WIDTH(DATA_WIDTH),
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.PACK_FACTOR(PACK_FACTOR),
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.PROCESS_MODE(PROCESS_MODE)
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) dut (
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.clk_in(clk),
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.rst(rst),
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.data_in(data_in),
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.out_of_range(out_of_range),
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tvalid(m_axis_tvalid)
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);
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// clock
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initial begin
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clk = 0;
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forever #(CLK_PERIOD/2) clk = ~clk;
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end
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integer i;
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initial begin
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clk = 0;
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rst = 1;
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data_in = 0;
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out_of_range = 0;
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#20;
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rst = 0;
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repeat(5) @(posedge clk);
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for (i = 1; i < 20; i++) begin
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@(posedge clk);
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data_in <= i;
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end
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#50;
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$finish;
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end
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always @(posedge clk) begin
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if (m_axis_tvalid) begin
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$display("TIME=%0t PACKED DATA = %h", $time, m_axis_tdata);
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end
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end
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endmodule |