346 lines
11 KiB
Systemverilog
346 lines
11 KiB
Systemverilog
`timescale 1ns / 1ps
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module tb_accumulator_top;
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localparam DATA_WIDTH = 12;
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localparam ACCUM_WIDTH = 32;
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localparam N_MAX = 4096;
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localparam WINDOW_SIZE = 65;
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localparam PACKET_SIZE = 1024;
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localparam READ_BATCH_SIZE = (PACKET_SIZE*8)/ACCUM_WIDTH;
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localparam MAX_WORDS = N_MAX;
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localparam MAX_SEQ_NUM = 64;
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logic clk_in;
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logic eth_clk_in;
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logic rst;
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logic [DATA_WIDTH-1:0] s_axis_tdata;
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logic s_axis_tvalid;
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logic start;
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logic [31:0] smp_num;
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logic [15:0] seq_num;
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logic req_ready;
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wire send_req;
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wire [7:0] m_axis_tdata;
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wire m_axis_tvalid;
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logic m_axis_tready;
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wire m_axis_tlast;
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wire finish;
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integer seed;
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integer total_errors;
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integer tests_total;
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integer tests_failed;
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integer tests_passed;
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integer packets_seen;
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integer current_packet_byte_count;
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integer total_words_captured;
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byte packet_bytes [0:PACKET_SIZE-1];
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logic [ACCUM_WIDTH-1:0] expected_words [0:MAX_WORDS-1];
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logic [ACCUM_WIDTH-1:0] captured_words_le[0:MAX_WORDS-1];
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logic [ACCUM_WIDTH-1:0] captured_words_be[0:MAX_WORDS-1];
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accumulator_top #(
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.DATA_WIDTH(DATA_WIDTH),
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.ACCUM_WIDTH(ACCUM_WIDTH),
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.N_MAX(N_MAX),
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.WINDOW_SIZE(WINDOW_SIZE),
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.PACKET_SIZE(PACKET_SIZE)
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) dut (
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.clk_in(clk_in),
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.rst(rst),
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tvalid(s_axis_tvalid),
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.start(start),
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.smp_num(smp_num),
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.seq_num(seq_num),
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.eth_clk_in(eth_clk_in),
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.req_ready(req_ready),
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.send_req(send_req),
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tvalid(m_axis_tvalid),
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.m_axis_tready(m_axis_tready),
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.m_axis_tlast(m_axis_tlast),
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.finish(finish)
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);
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initial begin
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clk_in = 1'b0;
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forever #5 clk_in = ~clk_in;
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end
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initial begin
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eth_clk_in = 1'b0;
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forever #4 eth_clk_in = ~eth_clk_in;
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end
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task automatic clear_scoreboard;
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integer i;
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begin
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packets_seen = 0;
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current_packet_byte_count = 0;
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total_words_captured = 0;
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for (i = 0; i < MAX_WORDS; i = i + 1) begin
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expected_words[i] = '0;
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captured_words_le[i] = '0;
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captured_words_be[i] = '0;
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end
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for (i = 0; i < PACKET_SIZE; i = i + 1)
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packet_bytes[i] = 8'h00;
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end
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endtask
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task automatic reset_dut;
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begin
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rst = 1'b1;
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start = 1'b0;
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s_axis_tdata = '0;
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s_axis_tvalid = 1'b0;
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smp_num = '0;
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seq_num = '0;
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req_ready = 1'b0;
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m_axis_tready = 1'b1;
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clear_scoreboard();
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repeat(12) @(posedge clk_in);
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rst = 1'b0;
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repeat(8) @(posedge clk_in);
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end
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endtask
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task automatic pulse_start;
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begin
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@(posedge clk_in);
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start <= 1'b1;
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@(posedge clk_in);
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start <= 1'b0;
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end
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endtask
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task automatic send_one_sample(input logic [DATA_WIDTH-1:0] val);
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begin
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@(posedge clk_in);
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s_axis_tdata <= val;
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s_axis_tvalid <= 1'b1;
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end
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endtask
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task automatic stop_stream;
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begin
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@(posedge clk_in);
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s_axis_tdata <= '0;
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s_axis_tvalid <= 1'b0;
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end
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endtask
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task automatic run_test(
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input integer test_id,
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input integer seq_num_i,
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input integer smp_num_i,
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input bit randomize_data,
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input integer base_value,
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input string test_name
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);
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logic [DATA_WIDTH-1:0] sample_mem [0:MAX_SEQ_NUM-1][0:(N_MAX*WINDOW_SIZE)-1];
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integer seq_idx;
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integer sample_idx;
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integer word_idx;
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integer k;
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integer exp_word_count;
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integer exp_packet_count;
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integer sample_value;
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integer local_sum;
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integer timeout_cnt;
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bit le_ok;
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bit be_ok;
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integer errors_before;
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integer i;
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begin
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tests_total = tests_total + 1;
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errors_before = total_errors;
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if (smp_num_i <= 0 || smp_num_i > N_MAX * WINDOW_SIZE || (smp_num_i % WINDOW_SIZE) != 0)
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$fatal(1, "[%0s] invalid smp_num=%0d", test_name, smp_num_i);
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if (seq_num_i <= 0 || seq_num_i > MAX_SEQ_NUM)
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$fatal(1, "[%0s] invalid seq_num=%0d", test_name, seq_num_i);
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$display("\n========================================");
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$display("TEST %0d: %0s", test_id, test_name);
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$display("seq_num=%0d smp_num=%0d randomize=%0d", seq_num_i, smp_num_i, randomize_data);
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$display("========================================");
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reset_dut();
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smp_num = smp_num_i;
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seq_num = seq_num_i;
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req_ready = 1'b1; // приемник готов заранее
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exp_word_count = smp_num_i / WINDOW_SIZE;
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exp_packet_count = (exp_word_count + READ_BATCH_SIZE - 1) / READ_BATCH_SIZE;
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for (seq_idx = 0; seq_idx < seq_num_i; seq_idx = seq_idx + 1) begin
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for (sample_idx = 0; sample_idx < smp_num_i; sample_idx = sample_idx + 1) begin
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if (randomize_data)
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sample_value = $unsigned($random(seed)) % (1 << DATA_WIDTH);
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else
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sample_value = (base_value + seq_idx * smp_num_i + sample_idx) % (1 << DATA_WIDTH);
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sample_mem[seq_idx][sample_idx] = sample_value[DATA_WIDTH-1:0];
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end
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end
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for (word_idx = 0; word_idx < exp_word_count; word_idx = word_idx + 1) begin
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local_sum = 0;
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for (seq_idx = 0; seq_idx < seq_num_i; seq_idx = seq_idx + 1) begin
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for (k = 0; k < WINDOW_SIZE; k = k + 1)
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local_sum = local_sum + sample_mem[seq_idx][word_idx * WINDOW_SIZE + k];
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end
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expected_words[word_idx] = local_sum[ACCUM_WIDTH-1:0];
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$display(" expected[%0d] = %0d (0x%08x)", word_idx, expected_words[word_idx], expected_words[word_idx]);
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end
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pulse_start();
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for (seq_idx = 0; seq_idx < seq_num_i; seq_idx = seq_idx + 1) begin
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for (sample_idx = 0; sample_idx < smp_num_i; sample_idx = sample_idx + 1)
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send_one_sample(sample_mem[seq_idx][sample_idx]);
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stop_stream();
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repeat(2) @(posedge clk_in);
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end
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timeout_cnt = 0;
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while (packets_seen < exp_packet_count && timeout_cnt < 50 * PACKET_SIZE) begin
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@(posedge eth_clk_in);
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timeout_cnt = timeout_cnt + 1;
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end
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if (packets_seen < exp_packet_count) begin
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$display("[%0s] ERROR: timeout waiting packets, got=%0d exp=%0d",
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test_name, packets_seen, exp_packet_count);
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total_errors = total_errors + 1;
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end
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timeout_cnt = 0;
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while (finish !== 1'b1 && timeout_cnt < 30000) begin
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@(posedge clk_in);
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timeout_cnt = timeout_cnt + 1;
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end
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if (finish !== 1'b1) begin
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$display("[%0s] ERROR: timeout waiting finish", test_name);
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total_errors = total_errors + 1;
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end
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le_ok = 1'b1;
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be_ok = 1'b1;
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for (i = 0; i < exp_word_count; i = i + 1) begin
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if (captured_words_le[i] !== expected_words[i]) le_ok = 1'b0;
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if (captured_words_be[i] !== expected_words[i]) be_ok = 1'b0;
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end
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if (!le_ok && !be_ok) begin
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$display("[%0s] ERROR: payload mismatch", test_name);
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for (i = 0; i < exp_word_count; i = i + 1)
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$display(" idx=%0d exp=0x%08x le=0x%08x be=0x%08x",
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i, expected_words[i], captured_words_le[i], captured_words_be[i]);
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total_errors = total_errors + 1;
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end else if (le_ok) begin
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$display("[%0s] payload check passed in little-endian", test_name);
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end else begin
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$display("[%0s] payload check passed in big-endian", test_name);
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end
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if (total_errors == errors_before) begin
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tests_passed = tests_passed + 1;
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$display("TEST %0d PASSED: %0s", test_id, test_name);
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end else begin
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tests_failed = tests_failed + 1;
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$display("TEST %0d FAILED: %0s", test_id, test_name);
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end
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req_ready = 1'b0;
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repeat(10) @(posedge clk_in);
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end
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endtask
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always @(posedge eth_clk_in) begin : CAPTURE_AXIS
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integer idx;
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logic [31:0] tmp_le;
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logic [31:0] tmp_be;
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if (rst) begin
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current_packet_byte_count = 0;
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end else if (m_axis_tvalid && m_axis_tready) begin
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if (current_packet_byte_count < PACKET_SIZE)
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packet_bytes[current_packet_byte_count] = m_axis_tdata;
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current_packet_byte_count = current_packet_byte_count + 1;
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if (m_axis_tlast) begin
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packets_seen = packets_seen + 1;
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if (current_packet_byte_count != PACKET_SIZE) begin
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$display("[packet] ERROR: packet size=%0d expected=%0d", current_packet_byte_count, PACKET_SIZE);
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total_errors = total_errors + 1;
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end
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for (idx = 0; idx < READ_BATCH_SIZE; idx = idx + 1) begin
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tmp_le = {
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packet_bytes[idx*4 + 3],
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packet_bytes[idx*4 + 2],
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packet_bytes[idx*4 + 1],
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packet_bytes[idx*4 + 0]
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};
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tmp_be = {
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packet_bytes[idx*4 + 0],
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packet_bytes[idx*4 + 1],
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packet_bytes[idx*4 + 2],
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packet_bytes[idx*4 + 3]
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};
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if (total_words_captured + idx < MAX_WORDS) begin
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captured_words_le[total_words_captured + idx] = tmp_le;
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captured_words_be[total_words_captured + idx] = tmp_be;
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end
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end
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total_words_captured = total_words_captured + READ_BATCH_SIZE;
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current_packet_byte_count = 0;
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end
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end
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end
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initial begin
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seed = 32'h1badf00d;
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total_errors = 0;
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tests_total = 0;
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tests_failed = 0;
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tests_passed = 0;
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reset_dut();
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run_test(1, 1, 1 * WINDOW_SIZE, 1'b0, 1, "deterministic_small");
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// $finish;
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run_test(2, 2, 1 * WINDOW_SIZE, 1'b1, 0, "random_seq3_smp8");
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run_test(3, 1, 16 * WINDOW_SIZE, 1'b1, 0, "random_seq5_smp16_multi_packet");
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run_test(4, 2, 12 * WINDOW_SIZE, 1'b1, 0, "random_seq7_smp12");
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run_test(5, 4, 256 * WINDOW_SIZE, 1'b1, 0, "random_max_smpnum");
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run_test(6, 2, 1500 * WINDOW_SIZE, 1'b1, 0, "random_max_smpnum2");
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$display("\n========================================");
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$display("ALL TESTS COMPLETED");
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$display("tests_total = %0d", tests_total);
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$display("tests_passed = %0d", tests_passed);
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$display("tests_failed = %0d", tests_failed);
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$display("total_errors = %0d", total_errors);
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$display("========================================");
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if (total_errors != 0)
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$fatal(1, "TB FAILED with %0d error(s)", total_errors);
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else
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$display("TB PASSED");
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$finish;
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end
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endmodule
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