120 lines
3.9 KiB
Systemverilog
120 lines
3.9 KiB
Systemverilog
module controller_wrapper_axil #(
|
|
parameter int unsigned DAC_DATA_WIDTH = 12,
|
|
parameter int unsigned ADDR_W = 16,
|
|
parameter int unsigned DATA_W = 32,
|
|
parameter int unsigned USER_W = 1
|
|
)
|
|
(
|
|
input logic ctrl_clk,
|
|
input logic dac_clk_in,
|
|
input logic adc_clk_in,
|
|
input logic rst_n,
|
|
axi4l_if.slave s_axil,
|
|
|
|
// adc_clk_in domain
|
|
input logic finish,
|
|
output logic [31:0] adc_window_size,
|
|
|
|
// dac_clk_in domain outputs
|
|
output logic [31:0] dac_pulse_width,
|
|
output logic [31:0] dac_pulse_period,
|
|
output logic [DAC_DATA_WIDTH-1:0] dac_pulse_height,
|
|
output logic [15:0] dac_pulse_num,
|
|
|
|
// adc_clk_in domain outputs
|
|
output logic [31:0] adc_pulse_period,
|
|
output logic [15:0] adc_pulse_num,
|
|
|
|
// pulse outputs
|
|
output logic dac_start,
|
|
output logic adc_start,
|
|
output logic dac_rst,
|
|
output logic adc_rst
|
|
);
|
|
|
|
logic start, rst_soft, send, cfg_bus_valid, busy;
|
|
logic [31:0] pulse_width, pulse_period, pulse_num, pulse_height_raw, pulse_period_ADC, window_size;
|
|
logic [7:0] error_code;
|
|
logic [31:0] desc_read_addr, desc_read_len, desc_read_config, status_read;
|
|
logic [31:0] desc_write_addr, desc_write_len_and_tag, status_write_len, status_write_config;
|
|
|
|
axi4l_reg_map_controller #(
|
|
.ADDR_W(ADDR_W),
|
|
.DATA_W(DATA_W),
|
|
.USER_W(USER_W)
|
|
) axi4l_reg_map_controller_inst (
|
|
.clk(ctrl_clk),
|
|
.rst_n(rst_n),
|
|
.s_axil(s_axil),
|
|
|
|
.start_o(start),
|
|
.cfg_bus_valid_o(cfg_bus_valid),
|
|
.send_o(send),
|
|
.pulse_width_o(pulse_width),
|
|
.pulse_period_o(pulse_period),
|
|
.pulse_num_o(pulse_num),
|
|
.pulse_height_raw_o(pulse_height_raw),
|
|
.pulse_period_ADC_o(pulse_period_ADC),
|
|
.window_size_o(window_size),
|
|
|
|
.desc_read_addr_o(desc_read_addr),
|
|
.desc_read_len_o(desc_read_len),
|
|
.desc_read_config_o(desc_read_config),
|
|
|
|
.status_read_i(status_read),
|
|
|
|
.desc_write_addr_o(desc_write_addr),
|
|
.desc_write_len_and_tag_o(desc_write_len_and_tag),
|
|
|
|
.status_write_len_i(status_write_len),
|
|
.status_write_config_i(status_write_config),
|
|
|
|
.rst_soft_o(rst_soft),
|
|
.busy_i(busy),
|
|
.error_code_i(error_code)
|
|
);
|
|
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Field layout inside cfg_bus:
|
|
// [31:0] pulse_width
|
|
// [63:32] pulse_period
|
|
// [79:64] pulse_num
|
|
// [95:80] pulse_height_raw[15:0]
|
|
// [127:96] pulse_period_ADC
|
|
// [159:128] window_size
|
|
// -------------------------------------------------------------------------
|
|
(* MARK_DEBUG="true" *) logic [159:0] cfg_bus;
|
|
assign cfg_bus = {window_size, pulse_period_ADC, pulse_height_raw[15:0], pulse_num[15:0], pulse_period, pulse_width};
|
|
|
|
control #(
|
|
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
|
)
|
|
controller (
|
|
.ctrl_clk(ctrl_clk),
|
|
.dac_clk_in(dac_clk_in),
|
|
.adc_clk_in(adc_clk_in),
|
|
.rst_n(rst_n),
|
|
.rst_soft(rst_soft),
|
|
.finish(finish),
|
|
.cfg_bus_input(cfg_bus),
|
|
.cfg_bus_valid(cfg_bus_valid),
|
|
.start(start),
|
|
|
|
.busy(busy),
|
|
|
|
.dac_pulse_width(dac_pulse_width),
|
|
.dac_pulse_period(dac_pulse_period),
|
|
.dac_pulse_height(dac_pulse_height),
|
|
.dac_pulse_num(dac_pulse_num),
|
|
.adc_pulse_period(adc_pulse_period),
|
|
.adc_pulse_num(adc_pulse_num),
|
|
.adc_window_size(adc_window_size),
|
|
.dac_start(dac_start),
|
|
.adc_start(adc_start),
|
|
.dac_rst(dac_rst),
|
|
.adc_rst(adc_rst)
|
|
);
|
|
|
|
|
|
endmodule |