59 lines
2.0 KiB
Systemverilog
59 lines
2.0 KiB
Systemverilog
// AN9767 model (1 port)
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module virtual_dac_model #(
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parameter int unsigned DAC_DATA_WIDTH = 14,
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// Bipolar output range: +/- VOLTAGE_RANGE
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parameter real VOLTAGE_RANGE = 5.0,
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// Analog output correction
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parameter real VOLTAGE_GAIN = 1.0,
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parameter real GROUND_BIAS = 0.0,
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// DAC timing parameters
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parameter time TRANSMISSION_DELAY = 150ps,
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parameter time CONVERSION_DELAY = 150ps
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)(
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input logic clk_i,
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input logic wrt_i,
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input logic [DAC_DATA_WIDTH-1:0] data_i,
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output real voltage_o
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);
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localparam int unsigned ZERO_CODE = (1 << (DAC_DATA_WIDTH - 1));
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localparam real VOLTAGE_STEP = (2 * VOLTAGE_RANGE) / real'((1 << DAC_DATA_WIDTH) - 1);
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logic [DAC_DATA_WIDTH-1:0] dac_code;
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//------------------------------------------------------------
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// Convert DAC code to analog voltage
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//------------------------------------------------------------
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function automatic real code_to_voltage( input logic [DAC_DATA_WIDTH-1:0] code);
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return (int'(code) - int'(ZERO_CODE)) * VOLTAGE_STEP;
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endfunction
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//------------------------------------------------------------
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// Initial state
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//------------------------------------------------------------
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initial begin
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dac_code = '0;
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voltage_o = code_to_voltage('0) * VOLTAGE_GAIN + GROUND_BIAS;
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end
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//------------------------------------------------------------
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// Latch new DAC code
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//------------------------------------------------------------
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always @(posedge wrt_i) begin
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dac_code <= #(TRANSMISSION_DELAY) data_i;
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end
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//------------------------------------------------------------
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// Update analog output
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//------------------------------------------------------------
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always @(posedge clk_i) begin
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voltage_o <= #(CONVERSION_DELAY) code_to_voltage(dac_code) * VOLTAGE_GAIN + GROUND_BIAS;
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end
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endmodule
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