Files
reflectometer_fpga_project/designs/reflectometer_base/debug.xdc
babintsev.lv 7665afd50b add: half-baked reflectometer TB
fix: constraints port names;
ready: reflectometer top module
2026-07-08 14:56:51 +03:00

4 lines
222 B
Tcl

# Primary clocks
create_clock -name ref_clock -period 5.000 [get_ports clk_in]
create_clock -name phy_rx_clock -period 8.000 [get_ports clk_m_axis]
create_clock -name phy_tx_clock -period 8.000 [get_ports clk_s_axis]