Files
reflectometer_fpga_project/designs/adc_dac_synchoronizer/debug.xdc
babintsev.lv 7665afd50b add: half-baked reflectometer TB
fix: constraints port names;
ready: reflectometer top module
2026-07-08 14:56:51 +03:00

3 lines
141 B
Tcl

# Primary clocks
create_clock -name eth_clk -period 8.000 [get_ports clk_dac]
create_clock -name acc_clk -period 15.385 [get_ports clk_adc]