127 lines
2.7 KiB
Systemverilog
127 lines
2.7 KiB
Systemverilog
`timescale 1ns / 1ps
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module generator_tb;
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parameter DATA_WIDTH = 14;
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parameter ZERO_LEVEL = 0;
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parameter CLK_PERIOD = 8;
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logic clk;
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logic rst;
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logic start;
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logic [31:0] pulse_width;
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logic [31:0] pulse_period;
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logic [DATA_WIDTH-1:0] pulse_height;
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logic [15:0] pulse_num;
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logic pulse;
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logic [DATA_WIDTH-1:0] pulse_height_out;
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logic sample_done, sample_req;
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// DUT
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generator #(
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.DATA_WIDTH(DATA_WIDTH),
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.ZERO_LEVEL(ZERO_LEVEL)
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) dut (
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.clk_in(clk),
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.rst(rst),
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.start(start),
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.pulse_width(pulse_width),
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.pulse_period(pulse_period),
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.pulse_height(pulse_height),
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.pulse_num(pulse_num),
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.pulse(pulse),
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.pulse_height_out(pulse_height_out),
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.sample_done(sample_done),
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.sample_req(sample_req)
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);
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// Clock
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initial begin
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clk = 0;
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forever #(CLK_PERIOD/2) clk = ~clk;
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end
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initial begin
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$display("\n=== GENERATOR TEST ===\n");
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rst = 1;
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start = 0;
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pulse_width = 0;
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pulse_period = 0;
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pulse_height = 0;
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pulse_num = 0;
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sample_done = 0;
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repeat(5) @(posedge clk);
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rst = 0;
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// --- Test 1 ---
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// 3 clk 1, 5 clk 0, 4 pulses
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repeat(2) @(posedge clk);
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pulse_width = 1;
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pulse_period = 20;
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pulse_num = 4;
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pulse_height = 14'h3FF;
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#1;
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start = 1;
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repeat(1) @(posedge clk);
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start = 0;
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wait(sample_req == 1);
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@(posedge clk);
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#1;
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sample_done = 1;
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wait(sample_req == 0)
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sample_done = 0;
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repeat(pulse_period*pulse_num+10) @(posedge clk);
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// // --- Test 2 ---
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// $display("\n--- SECOND RUN ---\n");
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// @(posedge clk);
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// pulse_width = 2;
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// pulse_period = 5;
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// pulse_num = 3;
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// pulse_height = 14'h155;
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// start = 1;
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// @(posedge clk);
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// start = 0;
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// repeat(40) @(posedge clk);
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// pulse_width = 3;
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// pulse_period = 8;
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// pulse_num = 4;
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// pulse_height = 14'h3FF;
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// start = 1;
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// repeat(1) @(posedge clk);
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// start = 0;
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// repeat(5) @(posedge clk);
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// start = 1;
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// pulse_height = 14'h155;
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// repeat(1) @(posedge clk);
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// start = 0;
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// repeat(50) @(posedge clk);
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// $display("\n=== TEST FINISHED ===");
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// $finish;
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end
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// // Display
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// always @(posedge clk) begin
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// $display("t=%0t | pulse=%0b | height=%h",
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// $time, pulse, pulse_height_out);
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// end
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endmodule |