13 lines
244 B
Systemverilog
13 lines
244 B
Systemverilog
module axis_defaults_master
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(
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axis_if.master axis
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);
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assign axis.req.t.keep = '1;
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assign axis.req.t.strb = '1;
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assign axis.req.t.last = 1'b1;
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assign axis.req.t.id = '0;
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assign axis.req.t.dest = '0;
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assign axis.req.t.user = '0;
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endmodule |