92 lines
2.1 KiB
Systemverilog
92 lines
2.1 KiB
Systemverilog
`timescale 1ns / 1ps
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module accumulator_top
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#(
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parameter DATA_WIDTH = 12,
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parameter ACCUM_WIDTH = 32,
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parameter N_MAX = 4096,
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parameter WINDOW_SIZE = 4,
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parameter PACKET_SIZE = 8,
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parameter READ_BATCH_SIZE =(PACKET_SIZE*8)/(ACCUM_WIDTH)
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)
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(
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// main clk
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input clk_in,
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input rst,
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// input data
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input [DATA_WIDTH-1:0] s_axis_tdata,
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input s_axis_tvalid,
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// parameters
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input start,
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input [31:0] smp_num,
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input [15:0] seq_num,
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// eth signals
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input eth_clk_in,
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input req_ready,
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output send_req,
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// output axis
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output logic [7:0] m_axis_tdata,
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output logic m_axis_tvalid,
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input logic m_axis_tready,
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output logic m_axis_tlast,
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output logic finish
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);
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wire [ACCUM_WIDTH-1:0] out_data;
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wire out_valid;
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wire readout_begin;
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wire batch_req;
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accumulator #(
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.DATA_WIDTH(DATA_WIDTH),
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.ACCUM_WIDTH(ACCUM_WIDTH),
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.N_MAX(N_MAX),
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.WINDOW_SIZE(WINDOW_SIZE),
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.PACKET_SIZE(PACKET_SIZE)
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) accum_main (
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.clk_in(clk_in),
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.rst(rst),
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tvalid(s_axis_tvalid),
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.start(start),
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.smp_num(smp_num),
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.seq_num(seq_num),
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.out_data(out_data),
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.out_valid(out_valid),
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.readout_begin(readout_begin),
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.batch_req(batch_req),
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.finish(finish)
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);
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out_axis_fifo #(
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.ACCUM_WIDTH(ACCUM_WIDTH),
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.WINDOW_SIZE(WINDOW_SIZE),
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.PACKET_SIZE(PACKET_SIZE)
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) output_async_fifo (
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.eth_clk_in (eth_clk_in),
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.acc_clk_in (clk_in),
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.rst (rst),
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.smp_num (smp_num),
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.m_axis_tdata (m_axis_tdata),
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.m_axis_tvalid (m_axis_tvalid),
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.m_axis_tready (m_axis_tready),
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.m_axis_tlast (m_axis_tlast),
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.acc_din (out_data),
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.din_valid (out_valid),
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.readout_begin (readout_begin),
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.req_ready (req_ready),
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.send_req (send_req),
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.batch_req (batch_req),
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.finish (finish)
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);
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endmodule |