253 lines
8.4 KiB
Systemverilog
253 lines
8.4 KiB
Systemverilog
`timescale 1 ns / 1 ns
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`include "interfaces.svh"
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module reflectometer_top #(
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parameter int unsigned DAC_DATA_WIDTH = 14,
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parameter int unsigned ADC_DATA_WIDTH = 12,
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parameter int unsigned PACK_FACTOR = 1,
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parameter int unsigned PROCESS_MODE = 0,
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parameter int unsigned ZERO_LEVEL = 8192,
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parameter int unsigned ACCUM_WIDTH = 32,
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parameter int unsigned N_MAX = 4096,
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parameter int unsigned PACKET_SIZE = 1024
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)(
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input wire clk_in,
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input wire rst_n,
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output wire locked,
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// Accumulator AXI-S bus
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input wire clk_axis_accumulator, // GMII PHY RX clock
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axis_if.master axis_accumulator,
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// Control AXI-S bus
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input wire clk_axis_control, // GMII PHY TX clock
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axis_if.slave axis_control,
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input wire [31:0] window_size, // New accum & old controller crutch
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// Status signals
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output wire workflow_done,
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output wire processing_done,
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// RTL-MAC handshake
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input wire request_ready,
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output wire send_request,
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// DAC
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output wire dac_clk_o,
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output wire [DAC_DATA_WIDTH-1:0] dac_data,
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output wire dac_wrt,
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// ADC
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output wire adc_clk_o,
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input wire [ADC_DATA_WIDTH-1:0] adc_data,
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input wire adc_otr
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);
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// -------------------------------------------------------------------------
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// Generated clocks for controller
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// Need to create this IP in Vivado:
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// input resetn
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// input clk_200 : 200 MHz : Reference clock
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// output clk_adc_65 : 65 MHz : ADC RTL clock
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// output clk_adc_65_180 : 65 MHz, phase 180 deg. : ADC PHY clock
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// output clk_adc_125 : 125 MHz : DAC RTL clock
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// output clk_adc_125_180 : 125 MHz, phase 180 deg. : DAC PHY clock
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// output locked
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// -------------------------------------------------------------------------
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wire clk_sampler, clk_generator, clk_locked;
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clk_wiz_ctrl_inst clk_wiz_inst
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(
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// Clock in ports
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.clk_200(clk_in),
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// Clock out ports
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.clk_adc_65(clk_sampler),
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.clk_adc_65_180(adc_clk_o),
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.clk_dac_125(clk_generator),
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.clk_dac_125_180(dac_clk_o),
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// Status and control signals
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.resetn(rst_n),
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.locked(clk_locked)
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);
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assign locked = clk_locked;
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// -------------------------------------------------------------------------
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// Controller reset
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// Use both external reset and clk_wiz lock
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// -------------------------------------------------------------------------
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wire ctrl_rst_n = rst_n & clk_locked;
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// -------------------------------------------------------------------------
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// Controller
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// -------------------------------------------------------------------------
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wire [31:0] dac_pulse_width;
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wire [31:0] dac_pulse_period;
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wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
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wire [15:0] dac_pulse_num;
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wire [31:0] adc_pulse_period;
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wire [15:0] adc_pulse_num;
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wire dac_start;
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wire adc_start;
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wire dac_rst;
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wire adc_rst;
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wire finish;
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control #(
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
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) udp_ctrl_inst (
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.eth_clk_in (clk_axis_control),
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.dac_clk_in (clk_generator),
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.adc_clk_in (clk_sampler),
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.rst_n (ctrl_rst_n),
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.s_axis_tdata (axis_control.tdata),
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.s_axis_tvalid (axis_control.tvalid),
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.s_axis_tready (axis_control.tready),
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.s_axis_tlast (axis_control.tlast),
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.finish (finish),
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.dac_pulse_width (dac_pulse_width),
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.dac_pulse_period (dac_pulse_period),
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.dac_pulse_height (dac_pulse_height),
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.dac_pulse_num (dac_pulse_num),
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.adc_pulse_period (adc_pulse_period),
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.adc_pulse_num (adc_pulse_num),
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.dac_start (dac_start),
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.adc_start (adc_start),
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.dac_rst (dac_rst),
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.adc_rst (adc_rst)
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);
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//------------------------------------------------------------
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// DAC -> ADC CDC
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//------------------------------------------------------------
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(* ASYNC_REG = "TRUE" *) logic [2:0] stretch; // 125/65~=2. Чтобы поймать единичный импульс, растянем его во времени
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(* ASYNC_REG = "TRUE" *) logic [1:0] sync_DA;
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wire dac_done_stretched;
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wire generator_done, generator_request;
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wire sampler_done, sampler_request;
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always_ff @(posedge clk_generator or posedge dac_rst)
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begin
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if (dac_rst)
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stretch <= 0;
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else begin
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stretch[0] <= generator_done;
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stretch[1] <= stretch[0];
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stretch[2] <= stretch[1];
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end
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end
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assign dac_done_stretched = |stretch;
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always_ff @(posedge clk_sampler or posedge adc_rst) begin
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if (adc_rst)
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sync_DA <= 0;
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else begin
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sync_DA[0] <= dac_done_stretched;
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sync_DA[1] <= sync_DA[0];
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end
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end
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assign sampler_request = sync_DA[1];
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//------------------------------------------------------------
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// ADC -> DAC CDC
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//------------------------------------------------------------
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(* ASYNC_REG = "TRUE" *) logic [1:0] sync_AD;
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always_ff @(posedge clk_generator or posedge dac_rst) begin
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if (dac_rst)
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sync_AD <= 0;
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else begin
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sync_AD[0] <= sampler_done;
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sync_AD[1] <= sync_AD[0];
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end
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end
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assign generator_request = sync_AD[1];
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//------------------------------------------------------------
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// Generator (DAC)
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//------------------------------------------------------------
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generator #(
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.DATA_WIDTH(DAC_DATA_WIDTH),
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.ZERO_LEVEL(ZERO_LEVEL)
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) generator_inst (
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.clk_dac(clk_generator),
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.rst(dac_rst),
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.start(dac_start),
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.pulse_width(dac_pulse_width),
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.pulse_period(dac_pulse_period),
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.pulse_height(dac_pulse_height),
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.pulse_num(dac_pulse_num),
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.dac_out(dac_data),
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.done(generator_done),
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.request(generator_request)
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);
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assign dac_wrt = dac_clk_o;
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// -------------------------------------------------------------------------
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// Sampler (ADC)
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// -------------------------------------------------------------------------
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wire [ADC_DATA_WIDTH*PACK_FACTOR-1:0] sampler_m_axis_tdata;
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wire sampler_m_axis_tvalid;
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sampler #(
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.DATA_WIDTH(ADC_DATA_WIDTH),
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.PACK_FACTOR(PACK_FACTOR),
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.PROCESS_MODE(PROCESS_MODE)
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) sampler_dut (
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.clk_in(clk_sampler),
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.rst(adc_rst),
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.data_in(adc_data),
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.out_of_range(adc_otr),
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.m_axis_tdata(sampler_m_axis_tdata),
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.m_axis_tvalid(sampler_m_axis_tvalid),
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.smp_num(adc_pulse_period),
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.done(sampler_done),
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.request(sampler_request)
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);
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// -------------------------------------------------------------------------
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// Accumulator
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// -------------------------------------------------------------------------
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assign workflow_done = finish;
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accumulator_top #(
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.DATA_WIDTH(ADC_DATA_WIDTH),
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.ACCUM_WIDTH(ACCUM_WIDTH),
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.N_MAX(N_MAX),
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.PACKET_SIZE(PACKET_SIZE)
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) accumulator_top_dut (
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.clk_in(clk_sampler),
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.rst(adc_rst),
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.s_axis_tdata(sampler_m_axis_tdata),
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.s_axis_tvalid(sampler_m_axis_tvalid),
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.start(adc_start),
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.smp_num(adc_pulse_period),
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.seq_num(adc_pulse_num),
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.window_size(window_size),
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.req_ready(request_ready),
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.send_req(send_request),
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.eth_clk_in(clk_axis_accumulator),
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.m_axis_tdata(axis_accumulator.tdata),
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.m_axis_tvalid(axis_accumulator.tvalid),
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.m_axis_tready(axis_accumulator.tready),
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.m_axis_tlast(axis_accumulator.tlast),
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.finish(finish), // full reflectometer workflow complete (with transaction)
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.accum_done(processing_done) // signal generation, sampling and processing complete
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);
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endmodule
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