267 lines
8.6 KiB
Systemverilog
267 lines
8.6 KiB
Systemverilog
`timescale 1ns / 1ps
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module tb_reflectometer;
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// parameters
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localparam int unsigned DAC_DATA_WIDTH = 14;
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localparam int unsigned ADC_DATA_WIDTH = 12;
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localparam PACK_FACTOR = 1; // not used in TB
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localparam PROCESS_MODE = 0; // 0 - uint, 1 - int
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localparam ZERO_LEVEL = 8192; // DAC zero voltage representation (2^14 / 2)
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localparam ACCUM_WIDTH = 32; // accumulator number bit witdth
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localparam N_MAX = 4096; // max value of windows to average by experiments
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localparam WINDOW_SIZE = 65; // fixed subwindow size to average by time
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localparam PACKET_SIZE = 1024; // bytes per UDP packet
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localparam int unsigned ADC_CLK_MHZ = 65;
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localparam int unsigned DAC_CLK_MHZ = 125;
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// may be changed for test purposes
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localparam int unsigned PULSE_WIDTH = 2**6;
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localparam int unsigned PULSE_PERIOD = 2**8;
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localparam int unsigned PULSE_NUM = 10;
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localparam int unsigned PULSE_HEIGHT = 2**12;
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localparam int unsigned PULSE_PERIOD_ADC = (int'(real'(ADC_CLK_MHZ) / real'(DAC_CLK_MHZ) * real'(PULSE_PERIOD)) / int'(WINDOW_SIZE)) * int'(WINDOW_SIZE);
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initial begin
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if (PULSE_WIDTH <= 0)
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$fatal(1, "PULSE_WIDTH should be positive");
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if (PULSE_PERIOD <= 0)
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$fatal(1, "PULSE_PERIOD should be positive");
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if (PULSE_NUM <= 0)
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$fatal(1, "PULSE_NUM should be positive");
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if (PULSE_HEIGHT <= 0)
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$fatal(1, "PULSE_HEIGHT should be positive");
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if (PULSE_WIDTH >= 2**32-1)
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$fatal(1, "PULSE_WIDTH too high");
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if (PULSE_PERIOD >= 2**32-1)
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$fatal(1, "PULSE_PERIOD too high");
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if (PULSE_NUM >= 2**16-1)
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$fatal(1, "PULSE_NUM too high");
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if (PULSE_HEIGHT >= 2**DAC_DATA_WIDTH-1)
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$fatal(1, "PULSE_HEIGHT too high");
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if (PULSE_PERIOD_ADC % WINDOW_SIZE == 0)
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$fatal(1, "PULSE_PERIOD_ADC isn't multiple of WINDOW_SIZE");
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end
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// DUT signals
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logic clk200, clk_eth_phy_tx, clk_eth_phy_rx; // GMII clocks
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logic rst_n;
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wire [3:0] status_leds; // [ None, dac_start, m_axis_valid, clk_wiz_locked ]
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wire dac_clk, dac_en;
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wire [DAC_DATA_WIDTH-1:0] dac_data;
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wire adc_clk;
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logic adc_otr;
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logic [ADC_DATA_WIDTH-1:0] adc_data;
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wire [7:0] s_axis_tx_tdata;
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wire s_axis_tx_tvalid;
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logic s_axis_tx_tready;
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wire s_axis_tx_tlast;
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logic phy_ready;
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wire accum_tx_start;
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logic [7:0] m_axis_rx_tdata;
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logic m_axis_rx_tvalid;
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logic m_axis_rx_tlast;
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logic m_axis_rx_tready;
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logic [127:0] dut_config = 0;
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// DUT
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reflectometer_top #(
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
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.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
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.PACK_FACTOR(PACK_FACTOR),
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.PROCESS_MODE(PROCESS_MODE),
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.ZERO_LEVEL(ZERO_LEVEL),
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.ACCUM_WIDTH(ACCUM_WIDTH),
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.N_MAX(N_MAX),
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.WINDOW_SIZE(WINDOW_SIZE),
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.PACKET_SIZE(PACKET_SIZE)
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) DUT (
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.sys_clk(clk200), // main clk 200 mhz
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.rst_n(rst_n), // rst_n
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.led(status_leds), // indication [3:0]
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.gmii_rx_clk(clk_eth_phy_rx), // ext. clk from PHY
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.gmii_tx_clk(clk_eth_phy_tx), // ext. clk from PHY
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// accumulated data stream
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.s_axis_tx_tdata(s_axis_tx_tdata),
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.s_axis_tx_tvalid(s_axis_tx_tvalid),
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.s_axis_tx_tready(s_axis_tx_tready),
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.s_axis_tx_tlast(s_axis_tx_tlast),
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// controller data stream
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.m_axis_rx_tdata(m_axis_rx_tdata),
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.m_axis_rx_tvalid(m_axis_rx_tvalid),
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.m_axis_rx_tlast(m_axis_rx_tlast),
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.m_axis_rx_tready(m_axis_rx_tready),
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.req_ready(phy_ready), // AXI-stream requester ready
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.send_req(accum_tx_start), // AXI-stream start transmit
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.p2_clk(dac_clk), // DAC clk
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.p2_data(dac_data), // DAC [DAC_DATA_WIDTH-1:0] data
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.p2_wrt(dac_en), // DAC write enable
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.ch2_clk(adc_clk), // ADC clk
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.ch2_data(adc_data), // ADC [ADC_DATA_WIDTH-1:0] data
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.ch2_otr(adc_otr) // ADC signal out-of-range
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);
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// clocks
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initial begin
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// 200 MHz
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clk200 = 1'b0;
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forever #2.5 clk200 = ~clk200;
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end
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initial begin
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// 125 MHz
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clk_eth_phy_tx = 1'b0;
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forever #4 clk_eth_phy_tx = ~clk_eth_phy_tx;
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end
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initial begin
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// 125 MHz
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clk_eth_phy_rx = 1'b0;
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forever #4 clk_eth_phy_rx = ~clk_eth_phy_rx;
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end
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// ADC input noise simulation
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always @(posedge adc_clk or negedge rst_n) begin
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if (!rst_n) begin
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adc_data <= '0;
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end else begin
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adc_data <= $urandom() & ((1 << ADC_DATA_WIDTH) - 1);
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end
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end
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assign adc_otr = 1'b0;
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// AXIS tasks
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task automatic axis_send_byte(
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ref logic clk,
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input logic [7:0] data,
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input logic last,
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ref logic tvalid,
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ref logic [7:0] tdata,
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ref logic tlast,
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input logic tready
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);
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@(posedge clk);
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tdata <= data;
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tlast <= last;
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tvalid <= 1'b1;
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// Ждем готовности приемника
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wait(tready === 1'b1);
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@(posedge clk);
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tvalid <= 1'b0;
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tlast <= 1'b0;
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endtask
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task automatic dut_soft_reset();
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axis_send_byte(
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.clk(clk_eth_phy_rx),
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.data(8'b00001111),
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.last(1'b1),
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.tvalid(m_axis_rx_tvalid),
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.tdata(m_axis_rx_tdata),
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.tlast(m_axis_rx_tlast),
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.tready(m_axis_rx_tready)
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);
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endtask
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task automatic dut_start();
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axis_send_byte(
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.clk(clk_eth_phy_rx),
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.data(8'b11110000),
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.last(1'b1),
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.tvalid(m_axis_rx_tvalid),
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.tdata(m_axis_rx_tdata),
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.tlast(m_axis_rx_tlast),
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.tready(m_axis_rx_tready)
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);
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endtask
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// task automatic dut_send_config(
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// input logic [127:0] ctrl_config
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// );
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// // команда set_data
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// axis_send_byte(
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// .clk(clk_eth_phy_rx),
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// .data(8'b10001000),
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// .last(1'b0),
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// .tvalid(m_axis_rx_tvalid),
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// .tdata(m_axis_rx_tdata),
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// .tlast(m_axis_rx_tlast),
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// .tready(m_axis_rx_tready)
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// );
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// // config burst
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// for (int i = 0; i < 16; i++) begin
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// logic [7:0] byte_to_send;
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// logic is_last;
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// // get byte
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// byte_to_send = ctrl_config[i*8 +: 8];
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// // tlast for last byte
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// is_last = (i == 15);
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// axis_send_byte(
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// .clk(clk_eth_phy_rx),
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// .data(byte_to_send),
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// .last(is_last),
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// .tvalid(m_axis_rx_tvalid),
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// .tdata(m_axis_rx_tdata),
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// .tlast(m_axis_rx_tlast),
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// .tready(m_axis_rx_tready)
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// );
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// end
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// endtask
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// some helpers for controller axis
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// GAME PLAN
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// 1. setup reflectometer
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// 2. create some reference signal with noise + virtual ADC
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// 3. setup m_axis endpoint for controller to start reflectometer (create multiple tasks)
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// 4. setup s_axis endpoint for data gathering and plotting
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// 5. check standalone reflectometer
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// 6. add reference signal averaging loop throw generator pulse posedge detection
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// 7. visual comparision of reference VS reflectometer
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// 8. add statistics for signal comparision (MSE/RMSE)
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// main TB
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initial begin
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// setup
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rst_n = 1'b0;
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s_axis_tx_tready = 1'b0;
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m_axis_rx_tdata = 1'b0;
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m_axis_rx_tvalid = 1'b0;
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m_axis_rx_tlast = 1'b0;
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phy_ready = 1'b0;
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// startup
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#100;
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rst_n = 1'b1;
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wait(DUT.clk_wiz_ctrl_inst.locked == 1'b1);
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#20;
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$display("=== clocks ready / wiz. locked ===");
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#40;
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// ready to work
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dut_config[31:0] = PULSE_WIDTH;
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dut_config[63:32] = PULSE_PERIOD;
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dut_config[79:64] = PULSE_NUM;
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dut_config[79+DAC_DATA_WIDTH:80] = PULSE_HEIGHT;
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dut_config[127:96] = PULSE_PERIOD_ADC;
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// dut_send_config(dut_config);
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dut_start();
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// dut_start();
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#1000;
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// dut_soft_reset();
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$display("=== ALL BASIC TESTS PASSED ===");
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$finish;
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end
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endmodule |