98 lines
4.3 KiB
Tcl
98 lines
4.3 KiB
Tcl
# === iostandard ===
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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# === SPI flash config ===
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
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# === clock config ===
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create_clock -period 5.000 [get_ports sys_clk_p]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
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set_property PACKAGE_PIN R4 [get_ports sys_clk_p]
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set_property PACKAGE_PIN T4 [get_ports sys_clk_n]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
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# === reset button ===
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set_property PACKAGE_PIN F15 [get_ports rst_n]
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set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
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# === status leds ===
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set_property PACKAGE_PIN L13 [get_ports {led[0]}]
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set_property PACKAGE_PIN M13 [get_ports {led[1]}]
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set_property PACKAGE_PIN K14 [get_ports {led[2]}]
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set_property PACKAGE_PIN K13 [get_ports {led[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[*]}]
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# === 1Gb ethernet PHY ===
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set_property PACKAGE_PIN P15 [get_ports rgmii_txc]
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set_property PACKAGE_PIN N14 [get_ports {rgmii_txd[0]}]
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set_property PACKAGE_PIN P16 [get_ports {rgmii_txd[1]}]
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set_property PACKAGE_PIN R17 [get_ports {rgmii_txd[2]}]
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set_property PACKAGE_PIN R16 [get_ports {rgmii_txd[3]}]
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set_property PACKAGE_PIN N17 [get_ports rgmii_txctl]
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set_property PACKAGE_PIN V18 [get_ports rgmii_rxc]
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set_property PACKAGE_PIN P19 [get_ports {rgmii_rxd[0]}]
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set_property PACKAGE_PIN U18 [get_ports {rgmii_rxd[1]}]
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set_property PACKAGE_PIN U17 [get_ports {rgmii_rxd[2]}]
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set_property PACKAGE_PIN P17 [get_ports {rgmii_rxd[3]}]
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set_property PACKAGE_PIN R19 [get_ports rgmii_rxctl]
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set_property PACKAGE_PIN N13 [get_ports e_mdc]
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set_property PACKAGE_PIN P14 [get_ports e_mdio]
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set_property PACKAGE_PIN R14 [get_ports e_reset]
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set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txc]
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set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[*]}]
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set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txctl]
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set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]
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set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[*]}]
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set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxctl]
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set_property IOSTANDARD LVCMOS33 [get_ports e_mdc]
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set_property IOSTANDARD LVCMOS33 [get_ports e_mdio]
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set_property IOSTANDARD LVCMOS33 [get_ports e_reset]
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set_property SLEW FAST [get_ports rgmii_txc]
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set_property SLEW FAST [get_ports rgmii_txctl]
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set_property SLEW FAST [get_ports {rgmii_txd[*]}]
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create_clock -period 8.000 [get_ports rgmii_rxc]
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# === DAC (J11 header) ===
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set_property IOSTANDARD LVCMOS33 [get_ports p2_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports p2_wrt]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[13]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[12]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[11]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[10]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[9]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[8]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[6]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[5]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[4]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[0]}]
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set_property SLEW FAST [get_ports p2_clk]
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set_property PACKAGE_PIN C18 [get_ports p2_clk]
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set_property PACKAGE_PIN C19 [get_ports p2_wrt]
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set_property PACKAGE_PIN B17 [get_ports {p2_data[13]}]
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set_property PACKAGE_PIN B18 [get_ports {p2_data[12]}]
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set_property PACKAGE_PIN D17 [get_ports {p2_data[11]}]
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set_property PACKAGE_PIN C17 [get_ports {p2_data[10]}]
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set_property PACKAGE_PIN A15 [get_ports {p2_data[9]}]
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set_property PACKAGE_PIN A16 [get_ports {p2_data[8]}]
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set_property PACKAGE_PIN B15 [get_ports {p2_data[7]}]
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set_property PACKAGE_PIN B16 [get_ports {p2_data[6]}]
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set_property PACKAGE_PIN A13 [get_ports {p2_data[5]}]
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set_property PACKAGE_PIN A14 [get_ports {p2_data[4]}]
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set_property PACKAGE_PIN E16 [get_ports {p2_data[3]}]
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set_property PACKAGE_PIN D16 [get_ports {p2_data[2]}]
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set_property PACKAGE_PIN C14 [get_ports {p2_data[1]}]
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set_property PACKAGE_PIN C15 [get_ports {p2_data[0]}]
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