TOPLEVEL_LANG = verilog
SIM ?= verilator

PWD := $(shell pwd)

WRAP_DIR = $(PWD)/../src
RTL_DIR  = $(PWD)/../../controller/src
LIBS_DIR = $(PWD)/../../../external/rtl_libs

VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
VERILOG_SOURCES += $(RTL_DIR)/dma_reg_pkg.sv
VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v
VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
VERILOG_SOURCES += $(RTL_DIR)/controller.sv
VERILOG_SOURCES += $(RTL_DIR)/dma_controller.sv
VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_desc.sv
VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_status.sv
VERILOG_SOURCES += $(RTL_DIR)/controller_wrapper_axil.sv
VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller_pkg.sv
VERILOG_SOURCES += $(RTL_DIR)/axis_defaults_helper.sv
VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller.sv
VERILOG_SOURCES += $(WRAP_DIR)/wrapper_controller_dma.sv
VERILOG_SOURCES += $(WRAP_DIR)/axi_dma_wrapper_if.sv
VERILOG_SOURCES += $(PWD)/tb_controller_dma_wrapper_axil.sv

TOPLEVEL = tb_controller_dma_wrapper_axil
MODULE = test_controller_and_dma


ifeq ($(SIM),verilator)
    EXTRA_ARGS += --trace --trace-structs
    EXTRA_ARGS += -I$(LIBS_DIR)/axi/rtl/
    COMPILE_ARGS += -Wno-fatal
    COMPILE_ARGS += -I$(LIBS_DIR)/axi/rtl/
    EXTRA_ARGS += --trace
    EXTRA_ARGS += --trace-structs
    EXTRA_ARGS += --public-flat-rw
    EXTRA_ARGS += -Wno-fatal
    EXTRA_ARGS += --timing
endif


include $(shell cocotb-config --makefiles)/Makefile.sim