# Primary clocks
create_clock -name geneartor_clk -period 8.000  [get_ports clk_dac]
create_clock -name sampler_clk -period 15.385  [get_ports clk_adc]
set_clock_groups -asynchronous -group [get_clocks geneartor_clk] -group [get_clocks sampler_clk]

# set_false_path -through [get_nets -hierarchical {*dac_signal* *internal_wire_singnal* *adc_singnal*}]
# set_false_path -through [get_nets {dac_done dac_done_stretched dac_request adc_done adc_request}]

# set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*pulse_height_reg*}]
# set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*dac_out_reg*}]
# Применяем к самому проводу сигнала CE, чтобы Vivado не дробила его
# set_property DONT_TOUCH true [get_nets -of_objects [get_pins -hierarchical -filter {PIN_NAME =~ *CE} -of_objects [get_cells *pulse_height_reg*]]]