`timescale 1ns / 1ps

module generator_tb;

    parameter DATA_WIDTH = 14;
    parameter ZERO_LEVEL = 0;
    parameter CLK_PERIOD = 8;

    logic clk;
    logic rst;
    logic start;

    logic [31:0] pulse_width;
    logic [31:0] pulse_period;
    logic [DATA_WIDTH-1:0] pulse_height;
    logic [15:0] pulse_num;

    wire pulse;
    wire [DATA_WIDTH-1:0] dac_out;
    wire sample_done;
    logic sample_req;

    // DUT
    generator #(
        .DATA_WIDTH(DATA_WIDTH),
        .ZERO_LEVEL(ZERO_LEVEL)
    ) dut (
        .clk_dac(clk),
        .rst(rst),
        .start(start),
        .pulse_width(pulse_width),
        .pulse_period(pulse_period),
        .pulse_height(pulse_height),
        .pulse_num(pulse_num),
        .dac_wrt(pulse),
        .dac_out(dac_out),
        .done(sample_done),
        .request(sample_req)
    );

    // Clock
    initial begin
        clk = 0;
        forever #(CLK_PERIOD/2) clk = ~clk;
    end

    initial begin
        $display("\n=== GENERATOR TEST ===\n");

        rst = 1;
        start = 0;

        pulse_width  = 0;
        pulse_period = 0;
        pulse_height = 0;
        pulse_num    = 0;
        sample_req   = 0;

        repeat(5) @(posedge clk);
        rst = 0;

       repeat(2) @(posedge clk);
        pulse_width  = 0;
        pulse_period = 20;
        pulse_num    = 4;
        pulse_height = 1024;

        // startup signal
        #1;
        start = 1;
        @(posedge clk);
        #1;
        start = 0;

        repeat(pulse_num) begin
            // syncronization
            wait(sample_done == 1);
            repeat(4) @(posedge clk);
            sample_req = 1;
            repeat(2) @(posedge clk);
            sample_req = 0;
        end
        wait(sample_done == 1);
    //     // --- Test 2 ---
    //     $display("\n--- SECOND RUN ---\n");

    //     @(posedge clk);
    //     pulse_width  = 2;
    //     pulse_period = 5;
    //     pulse_num    = 3;
    //     pulse_height = 14'h155;
    //     start = 1;

    //     @(posedge clk);
    //     start = 0;

    //     repeat(40) @(posedge clk);
        
    //     pulse_width  = 3;
    //     pulse_period = 8;
    //     pulse_num    = 4;
    //     pulse_height = 14'h3FF;
    //     start = 1;

    //    repeat(1) @(posedge clk);
    //     start = 0;
        
    //     repeat(5) @(posedge clk);
    //     start = 1;
    //     pulse_height = 14'h155;

    //    repeat(1) @(posedge clk);
    //     start = 0;
        
    //     repeat(50) @(posedge clk);


    //     $display("\n=== TEST FINISHED ===");
    #100;
    $finish;
    end

    // // Display
    // always @(posedge clk) begin
    //     $display("t=%0t | pulse=%0b | height=%h",
    //               $time, pulse, pulse_height_out);
    // end

endmodule