# SPDX-License-Identifier: MIT
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#

# FPGA settings
FPGA_PART = xc7a35tfgg484-1
FPGA_TOP = accumulator_top
FPGA_ARCH = artix7

RTL_DIR = ../src

# Simulation settings
SIM_TOP     = tb_accumulator_top
SIM_RUNTIME ?= 10000 us

# Design sources only
SYN_FILES += $(filter-out %_tb.sv,$(sort $(shell find $(RTL_DIR) -type f -name '*.v' -o -type f -name '*.sv')))

# Testbench sources. Vivado puts these into "sim_1", Questa compiles them into "work".
TB_FILES += out_axis_fifo_tb.sv
TB_FILES += accum_full_tb.sv

XCI_FILES = $(sort $(shell find $(RTL_DIR) -type f -name '*.xci'))

XDC_FILES += ../../../constraints/ax7a035b.xdc
XDC_FILES += test_timing.xdc

include ../../../scripts/vivado.mk
include ../../../scripts/questa.mk

program: $(PROJECT).bit
	echo "open_hw_manager" > program.tcl
	echo "connect_hw_server" >> program.tcl
	echo "open_hw_target" >> program.tcl
	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
	echo "program_hw_devices [current_hw_device]" >> program.tcl
	echo "exit" >> program.tcl
	vivado -nojournal -nolog -mode batch -source program.tcl

$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
	echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
	echo "exit" >> generate_mcs.tcl
	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
	mkdir -p rev
	COUNT=100; \
	while [ -e rev/$*_rev$$COUNT.bit ]; \
	do COUNT=$$((COUNT+1)); done; \
	COUNT=$$((COUNT-1)); \
	for x in .mcs .prm; \
	do cp $*$$x rev/$*_rev$$COUNT$$x; \
	echo "Output: rev/$*_rev$$COUNT$$x"; done;