module tb_controller_wrapper_axil #(
  parameter int unsigned DAC_DATA_WIDTH = 12,
  parameter int unsigned ADDR_W = 16,
  parameter int unsigned DATA_W = 32,
  parameter int unsigned USER_W = 1
)(
  input  logic                 ctrl_clk,
  input  logic                 rst,

  input  logic [ADDR_W-1:0]   s_axil_awaddr,
  input  logic [2:0]          s_axil_awprot,
  input  logic                s_axil_awvalid,
  output logic                s_axil_awready,

  input  logic [DATA_W-1:0]   s_axil_wdata,
  input  logic [DATA_W/8-1:0] s_axil_wstrb,
  input  logic                s_axil_wvalid,
  output logic                s_axil_wready,

  output logic [1:0]          s_axil_bresp,
  output logic                s_axil_bvalid,
  input  logic                s_axil_bready,

  input  logic [ADDR_W-1:0]   s_axil_araddr,
  input  logic [2:0]          s_axil_arprot,
  input  logic                s_axil_arvalid,
  output logic                s_axil_arready,

  output logic [DATA_W-1:0]   s_axil_rdata,
  output logic [1:0]          s_axil_rresp,
  output logic                s_axil_rvalid,
  input  logic                s_axil_rready
);

  logic rst_n;
  assign rst_n = ~rst;

  logic dac_clk_in;
  logic adc_clk_in;
  assign dac_clk_in = ctrl_clk;
  assign adc_clk_in = ctrl_clk;

  logic finish;
  assign finish = 1'b0;

  axi4l_if #(
    .ADDR_W(ADDR_W),
    .DATA_W(DATA_W),
    .USER_W(USER_W)
  ) axil_bus (
    .aclk(ctrl_clk),
    .aresetn(rst_n)
  );

  axi4l_flat_to_if #(
    .ADDR_W(ADDR_W),
    .DATA_W(DATA_W),
    .USER_W(USER_W)
  ) u_flat_to_if (
    .s_axil_awaddr (s_axil_awaddr),
    .s_axil_awprot (s_axil_awprot),
    .s_axil_awvalid(s_axil_awvalid),
    .s_axil_awready(s_axil_awready),

    .s_axil_wdata  (s_axil_wdata),
    .s_axil_wstrb  (s_axil_wstrb),
    .s_axil_wvalid (s_axil_wvalid),
    .s_axil_wready (s_axil_wready),

    .s_axil_bresp  (s_axil_bresp),
    .s_axil_bvalid (s_axil_bvalid),
    .s_axil_bready (s_axil_bready),

    .s_axil_araddr (s_axil_araddr),
    .s_axil_arprot (s_axil_arprot),
    .s_axil_arvalid(s_axil_arvalid),
    .s_axil_arready(s_axil_arready),

    .s_axil_rdata  (s_axil_rdata),
    .s_axil_rresp  (s_axil_rresp),
    .s_axil_rvalid (s_axil_rvalid),
    .s_axil_rready (s_axil_rready),

    .m_axil(axil_bus)
  );

  logic [31:0]               adc_window_size;
  logic [31:0]               dac_pulse_width;
  logic [31:0]               dac_pulse_period;
  logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
  logic [15:0]               dac_pulse_num;
  logic [31:0]               adc_pulse_period;
  logic [15:0]               adc_pulse_num;
  logic                      dac_start;
  logic                      adc_start;
  logic                      dac_rst;
  logic                      adc_rst;

  controller_wrapper_axil #(
    .DAC_DATA_WIDTH(DAC_DATA_WIDTH),
    .ADDR_W(ADDR_W),
    .DATA_W(DATA_W),
    .USER_W(USER_W)
  ) dut (
    .ctrl_clk(ctrl_clk),
    .dac_clk_in(dac_clk_in),
    .adc_clk_in(adc_clk_in),
    .rst_n(rst_n),
    .s_axil(axil_bus),

    .finish(finish),
    .adc_window_size(adc_window_size),

    .dac_pulse_width(dac_pulse_width),
    .dac_pulse_period(dac_pulse_period),
    .dac_pulse_height(dac_pulse_height),
    .dac_pulse_num(dac_pulse_num),

    .adc_pulse_period(adc_pulse_period),
    .adc_pulse_num(adc_pulse_num),

    .dac_start(dac_start),
    .adc_start(adc_start),
    .dac_rst(dac_rst),
    .adc_rst(adc_rst)
  );

endmodule