`timescale 1ns / 1ps

module sampler_tb;

    parameter DATA_WIDTH = 12;
    parameter PACK_FACTOR = 3;
    parameter PROCESS_MODE = 0;
    
    parameter CLK_PERIOD = 15.3846; 

    logic clk;
    logic rst;
    logic [DATA_WIDTH-1:0] data_in;
    logic out_of_range;

    logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
    logic m_axis_tvalid;

    // DUT
    sampler #(
        .DATA_WIDTH(DATA_WIDTH),
        .PACK_FACTOR(PACK_FACTOR),
        .PROCESS_MODE(PROCESS_MODE)
    ) dut (
        .clk_in(clk),
        .rst(rst),
        .data_in(data_in),
        .out_of_range(out_of_range),
        .m_axis_tdata(m_axis_tdata),
        .m_axis_tvalid(m_axis_tvalid)
    );

    // clock
     initial begin
        clk = 0;
        forever #(CLK_PERIOD/2) clk = ~clk;
    end

    integer i;

    initial begin
        clk = 0;
        rst = 1;
        data_in = 0;
        out_of_range = 0;

        #20;
        rst = 0;
        repeat(5) @(posedge clk);

        for (i = 1; i < 20; i++) begin
            @(posedge clk);

            data_in <= i;
        end

        #50;
        $finish;
    end

    always @(posedge clk) begin
        if (m_axis_tvalid) begin
            $display("TIME=%0t PACKED DATA = %h", $time, m_axis_tdata);
        end
    end

endmodule