# === iostandard === set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] # === SPI flash config === set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] # === clock config === create_clock -period 5.000 [get_ports sys_clk_p] set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p] set_property PACKAGE_PIN R4 [get_ports sys_clk_p] set_property PACKAGE_PIN T4 [get_ports sys_clk_n] set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n] # === reset button === set_property IOSTANDARD LVCMOS15 [get_ports rst_n] set_property PACKAGE_PIN T6 [get_ports rst_n] # === leds === set_property IOSTANDARD LVCMOS33 [get_ports {led[*]}] set_property PACKAGE_PIN C17 [get_ports {led[0]}] set_property PACKAGE_PIN D17 [get_ports {led[1]}] set_property PACKAGE_PIN V20 [get_ports {led[2]}] set_property PACKAGE_PIN U20 [get_ports {led[3]}] # === 1Gb ethernet PHY === set_property PACKAGE_PIN V10 [get_ports e_mdio] set_property IOSTANDARD LVCMOS33 [get_ports e_mdio] set_property PACKAGE_PIN W10 [get_ports e_mdc] set_property IOSTANDARD LVCMOS33 [get_ports e_mdc] set_property PULLTYPE PULLUP [get_ports e_mdc] set_property SLEW SLOW [get_ports e_mdio] set_property PULLTYPE PULLUP [get_ports e_mdio] # eth rx create_clock -period 8.000 -name rx_clk [get_ports e_rxc] set_property IOSTANDARD LVCMOS33 [get_ports e_rxc] set_property PACKAGE_PIN K18 [get_ports e_rxc] set_property IOSTANDARD LVCMOS33 [get_ports e_rxdv] set_property PACKAGE_PIN M22 [get_ports e_rxdv] set_property IOSTANDARD LVCMOS33 [get_ports e_rxer] set_property PACKAGE_PIN N19 [get_ports e_rxer] set_property IOSTANDARD LVCMOS33 [get_ports {e_rxd[*]}] set_property PACKAGE_PIN N22 [get_ports {e_rxd[0]}] set_property PACKAGE_PIN H18 [get_ports {e_rxd[1]}] set_property PACKAGE_PIN H17 [get_ports {e_rxd[2]}] set_property PACKAGE_PIN K19 [get_ports {e_rxd[3]}] set_property PACKAGE_PIN M21 [get_ports {e_rxd[4]}] set_property PACKAGE_PIN L21 [get_ports {e_rxd[5]}] set_property PACKAGE_PIN N20 [get_ports {e_rxd[6]}] set_property PACKAGE_PIN M20 [get_ports {e_rxd[7]}] # eth tx set_property IOSTANDARD LVCMOS33 [get_ports e_txc] set_property PACKAGE_PIN J17 [get_ports e_txc] set_property IOSTANDARD LVCMOS33 [get_ports e_gtxc] set_property PACKAGE_PIN L18 [get_ports e_gtxc] set_property IOSTANDARD LVCMOS33 [get_ports e_txen] set_property PACKAGE_PIN M16 [get_ports e_txen] set_property IOSTANDARD LVCMOS33 [get_ports e_txer] set_property PACKAGE_PIN M13 [get_ports e_txer] set_property IOSTANDARD LVCMOS33 [get_ports {e_txd[*]}] set_property PACKAGE_PIN M15 [get_ports {e_txd[0]}] set_property PACKAGE_PIN L14 [get_ports {e_txd[1]}] set_property PACKAGE_PIN K16 [get_ports {e_txd[2]}] set_property PACKAGE_PIN L16 [get_ports {e_txd[3]}] set_property PACKAGE_PIN K17 [get_ports {e_txd[4]}] set_property PACKAGE_PIN L20 [get_ports {e_txd[5]}] set_property PACKAGE_PIN L19 [get_ports {e_txd[6]}] set_property PACKAGE_PIN L13 [get_ports {e_txd[7]}] set_property IOSTANDARD LVCMOS33 [get_ports e_reset] set_property PACKAGE_PIN L15 [get_ports e_reset] create_clock -period 8.000 -name tx_clk [get_ports e_gtxc] set_false_path -reset_path -from [get_clocks sys_clk_p] -to [get_clocks rx_clk] # === ADC an9238 (J4 header) === set_property PACKAGE_PIN K14 [get_ports ch2_clk] set_property PACKAGE_PIN K13 [get_ports ch2_data[0]] set_property PACKAGE_PIN H14 [get_ports ch2_data[1]] set_property PACKAGE_PIN J14 [get_ports ch2_data[2]] set_property PACKAGE_PIN H15 [get_ports ch2_data[3]] set_property PACKAGE_PIN J15 [get_ports ch2_data[4]] set_property PACKAGE_PIN G13 [get_ports ch2_data[5]] set_property PACKAGE_PIN H13 [get_ports ch2_data[6]] set_property PACKAGE_PIN J21 [get_ports ch2_data[7]] set_property PACKAGE_PIN J20 [get_ports ch2_data[8]] set_property PACKAGE_PIN G16 [get_ports ch2_data[9]] set_property PACKAGE_PIN G15 [get_ports ch2_data[10]] set_property PACKAGE_PIN H19 [get_ports ch2_data[11]] set_property PACKAGE_PIN J19 [get_ports ch2_otr] set_property PACKAGE_PIN J16 [get_ports ch1_data[1]] set_property PACKAGE_PIN F15 [get_ports ch1_data[0]] set_property PACKAGE_PIN K22 [get_ports ch1_data[3]] set_property PACKAGE_PIN K21 [get_ports ch1_data[2]] set_property PACKAGE_PIN H22 [get_ports ch1_data[5]] set_property PACKAGE_PIN J22 [get_ports ch1_data[4]] set_property PACKAGE_PIN G20 [get_ports ch1_data[7]] set_property PACKAGE_PIN H20 [get_ports ch1_data[6]] set_property PACKAGE_PIN G22 [get_ports ch1_data[9]] set_property PACKAGE_PIN G21 [get_ports ch1_data[8]] set_property PACKAGE_PIN D22 [get_ports ch1_data[11]] set_property PACKAGE_PIN E22 [get_ports ch1_data[10]] set_property PACKAGE_PIN D21 [get_ports ch1_clk] set_property PACKAGE_PIN E21 [get_ports ch1_otr] set_property IOSTANDARD LVCMOS33 [get_ports ch2_clk] set_property IOSTANDARD LVCMOS33 [get_ports {ch2_data[*]}] set_property IOSTANDARD LVCMOS33 [get_ports ch2_otr] set_property IOSTANDARD LVCMOS33 [get_ports {ch1_data[*]}] set_property IOSTANDARD LVCMOS33 [get_ports ch1_clk] set_property IOSTANDARD LVCMOS33 [get_ports ch1_otr] set_property SLEW FAST [get_ports {ch2_clk ch1_clk}] # === DAC an9767(J5 header) === set_property PACKAGE_PIN F13 [get_ports {da1_clk}] set_property PACKAGE_PIN F14 [get_ports {da1_wrt}] set_property PACKAGE_PIN AB15 [get_ports {da1_data[13]}] set_property PACKAGE_PIN AA15 [get_ports {da1_data[12]}] set_property PACKAGE_PIN AA14 [get_ports {da1_data[11]}] set_property PACKAGE_PIN Y13 [get_ports {da1_data[10]}] set_property PACKAGE_PIN AB17 [get_ports {da1_data[9]}] set_property PACKAGE_PIN AB16 [get_ports {da1_data[8]}] set_property PACKAGE_PIN AA16 [get_ports {da1_data[7]}] set_property PACKAGE_PIN Y16 [get_ports {da1_data[6]}] set_property PACKAGE_PIN AB12 [get_ports {da1_data[5]}] set_property PACKAGE_PIN AB11 [get_ports {da1_data[4]}] set_property PACKAGE_PIN Y14 [get_ports {da1_data[3]}] set_property PACKAGE_PIN W14 [get_ports {da1_data[2]}] set_property PACKAGE_PIN C19 [get_ports {da1_data[1]}] set_property PACKAGE_PIN C18 [get_ports {da1_data[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {da1_data[*]}] set_property IOSTANDARD LVCMOS33 [get_ports {da1_wrt}] set_property IOSTANDARD LVCMOS33 [get_ports {da1_clk}] set_property PACKAGE_PIN E14 [get_ports {da2_clk}] set_property PACKAGE_PIN E13 [get_ports {da2_wrt}] set_property PACKAGE_PIN D15 [get_ports {da2_data[13]}] set_property PACKAGE_PIN D14 [get_ports {da2_data[12]}] set_property PACKAGE_PIN B13 [get_ports {da2_data[11]}] set_property PACKAGE_PIN C13 [get_ports {da2_data[10]}] set_property PACKAGE_PIN AB13 [get_ports {da2_data[9]}] set_property PACKAGE_PIN AA13 [get_ports {da2_data[8]}] set_property PACKAGE_PIN A19 [get_ports {da2_data[7]}] set_property PACKAGE_PIN A18 [get_ports {da2_data[6]}] set_property PACKAGE_PIN E18 [get_ports {da2_data[5]}] set_property PACKAGE_PIN F18 [get_ports {da2_data[4]}] set_property PACKAGE_PIN F20 [get_ports {da2_data[3]}] set_property PACKAGE_PIN F19 [get_ports {da2_data[2]}] set_property PACKAGE_PIN A20 [get_ports {da2_data[1]}] set_property PACKAGE_PIN B20 [get_ports {da2_data[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {da2_clk}] set_property IOSTANDARD LVCMOS33 [get_ports {da2_wrt}] set_property IOSTANDARD LVCMOS33 [get_ports {da2_data[*]}]