import dma_reg_pkg::*; module dma_controller ( input dma_clk, input rst_n, input logic send_desc_read, input logic send_desc_write, input logic take_status_read, input logic take_status_write, input logic ready_desc_read, input logic ready_desc_write, output logic ready_status_read, output logic ready_status_write, input dma_read_desc_t desc_read_cmd, input dma_write_desc_t desc_write_cmd, output dma_read_status_t status_read_cmd, output dma_write_status_t status_write_cmd, input dma_read_status_t status_read_cmd_in, input dma_write_status_t status_write_cmd_in, output logic desc_read_dma_busy, output logic desc_write_dma_busy, output logic status_read_dma_busy, output logic status_write_dma_busy, output logic desc_read_dma_hs, output logic desc_write_dma_hs, output logic status_read_dma_hs, output logic status_write_dma_hs, output logic valid_desc_read, output logic valid_desc_write, input logic valid_status_read, input logic valid_status_write, output dma_read_desc_t desc_read_cmd_out, output dma_write_desc_t desc_write_cmd_out ); shaper_axis_desc #( .DATA_WIDTH($bits(dma_read_desc_t)) ) shaper_axis_desc_read ( .clk(dma_clk), .rst_n(rst_n), .data_in(desc_read_cmd), .send(send_desc_read), .ready(ready_desc_read), .busy(desc_read_dma_busy), .handshake(desc_read_dma_hs), .data_out(desc_read_cmd_out), .valid(valid_desc_read) ); shaper_axis_desc #( .DATA_WIDTH($bits(dma_write_desc_t)) ) shaper_axis_desc_write ( .clk(dma_clk), .rst_n(rst_n), .data_in(desc_write_cmd), .send(send_desc_write), .ready(ready_desc_write), .busy(desc_write_dma_busy), .handshake(desc_write_dma_hs), .data_out(desc_write_cmd_out), .valid(valid_desc_write) ); shaper_axis_status #( .DATA_WIDTH($bits(dma_read_status_t)) ) shaper_axis_status_read ( .clk(dma_clk), .rst_n(rst_n), .data_in(status_read_cmd_in), .take(take_status_read), .valid(valid_status_read), .ready(ready_status_read), .busy(status_read_dma_busy), .handshake(status_read_dma_hs), .data_out(status_read_cmd) ); shaper_axis_status #( .DATA_WIDTH($bits(dma_write_status_t)) ) shaper_axis_status_write ( .clk(dma_clk), .rst_n(rst_n), .data_in(status_write_cmd_in), .take(take_status_write), .valid(valid_status_write), .ready(ready_status_write), .busy(status_write_dma_busy), .handshake(status_write_dma_hs), .data_out(status_write_cmd) ); endmodule