`timescale 1ns / 1ps

module accumulator_top
#(
    parameter DATA_WIDTH = 12,
    parameter ACCUM_WIDTH = 32,
    parameter N_MAX = 4096,
    parameter PACKET_SIZE = 1024,
    parameter READ_BATCH_SIZE =(PACKET_SIZE*8)/(ACCUM_WIDTH)
    )
(
    // main clk
    input clk_in,
    input rst,
    
    // input data
    input [DATA_WIDTH-1:0] s_axis_tdata,
    input s_axis_tvalid,

    // parameters
    input start,
    input [31:0] smp_num,
    input [15:0] seq_num,
    input [31:0] window_size,

    // eth signals
    input eth_clk_in,
    input req_ready,
    output send_req,

    // output axis
    output logic [7:0]      m_axis_tdata,
    output logic            m_axis_tvalid,
    input  logic            m_axis_tready,
    output logic            m_axis_tlast,

    output logic finish
    );

    wire [ACCUM_WIDTH-1:0] out_data;
    wire out_valid;
    wire readout_begin;
    wire batch_req;

    logic finish_int;
    logic finish_int_d;
    logic finish_pulse;
    logic calc_active;
    logic start_accept;
    logic [31:0] window_size_reg;

    wire [31:0] window_size_safe = (window_size == 32'd0) ? 32'd1 : window_size;

    assign finish_pulse = finish_int && !finish_int_d;
    assign start_accept = start && !calc_active;
    assign finish = finish_int;

    // Keep the top copy stable for blocks that start later than the accum itself
    always_ff @(posedge clk_in) begin
        if (rst) begin
            calc_active     <= 1'b0;
            finish_int_d    <= 1'b0;
            window_size_reg <= 32'd1;
        end else begin
            finish_int_d <= finish_int;

            if (start_accept) begin
                calc_active     <= 1'b1;
            end else if (finish_pulse) begin
                calc_active <= 1'b0;
            end
        end
    end

    accumulator #(
        .DATA_WIDTH(DATA_WIDTH),
        .ACCUM_WIDTH(ACCUM_WIDTH),
        .N_MAX(N_MAX),
        .PACKET_SIZE(PACKET_SIZE)
    ) accum_main (
        .clk_in(clk_in),
        .rst(rst),
        .s_axis_tdata(s_axis_tdata),
        .s_axis_tvalid(s_axis_tvalid),
        .start(start_accept),
        .smp_num(smp_num),
        .seq_num(seq_num),
        .window_size(window_size),
        .out_data(out_data),
        .out_valid(out_valid),
        .readout_begin(readout_begin),
        .batch_req(batch_req),
        .finish(finish_int)
    );

    out_axis_fifo #(
        .ACCUM_WIDTH(ACCUM_WIDTH),
        .PACKET_SIZE(PACKET_SIZE)
    ) output_async_fifo (
        .eth_clk_in    (eth_clk_in),
        .acc_clk_in    (clk_in),
        .rst           (rst),
        .smp_num       (smp_num),
        .window_size   (window_size_reg),

        .m_axis_tdata  (m_axis_tdata),
        .m_axis_tvalid (m_axis_tvalid),
        .m_axis_tready (m_axis_tready),
        .m_axis_tlast  (m_axis_tlast),

        .acc_din       (out_data),
        .din_valid     (out_valid),

        .readout_begin (readout_begin),

        .req_ready     (req_ready),
        .send_req      (send_req),

        .batch_req     (batch_req),
        .finish        (finish_int)
    );
endmodule