`timescale 1ns / 1ps


module adder
#(
    parameter DATA_WIDTH = 12,
    parameter ACCUM_WIDTH = 32
    )
(
    input clk_in,
    input rst,
    input start,
    input [31:0] window_size,
    input [DATA_WIDTH-1:0] s_axis_tdata,
    input s_axis_tvalid,
    
    output [ACCUM_WIDTH-1:0] sum_data,
    output sum_valid
    );

    logic [ACCUM_WIDTH-1:0] accum, res;
    logic [DATA_WIDTH-1:0] axis_data;
    logic res_valid, axis_valid;
    (* MARK_DEBUG = "TRUE" *) logic [31:0] cnt;
    logic [31:0] window_size_reg;

    wire [31:0] window_size_safe = (window_size == 32'd0) ? 32'd1 : window_size;
    
    always @(posedge clk_in) begin
        if (rst) begin
            accum <= '0;
            cnt <= '0;
            res <= '0;
            res_valid <= 0;
            axis_data <= '0;
            axis_valid <= 0;
            window_size_reg <= 32'd1;
        end else begin
            res_valid <= 0;

            if (start) begin
                accum <= '0;
                cnt <= '0;
                res <= '0;
                axis_data <= '0;
                axis_valid <= 0;
                window_size_reg <= window_size_safe;
            end else begin
                axis_data <= s_axis_tdata;
                axis_valid <= s_axis_tvalid;
                if (axis_valid) begin
                    if (cnt == window_size_reg - 1) begin
                        res <= accum + axis_data;
                        res_valid <= 1;
                        accum <= '0;
                        cnt <= '0;
                    end else begin
                        accum <= accum + axis_data;
                        cnt   <= cnt + 1;
                    end
                end
            end
        end
    end 
   
    assign sum_valid = res_valid;
    assign sum_data = res;
    
endmodule