`timescale 1ns / 1ps



module sampler
#(
    parameter DATA_WIDTH = 12,
    parameter PACK_FACTOR = 1,
    parameter PROCESS_MODE = 0
    )
(
    input clk_in,
    input rst,
    input [DATA_WIDTH-1:0] data_in,
    input out_of_range,

    output logic [DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata,
    output logic                              m_axis_tvalid
    );
    logic [DATA_WIDTH-1:0] data_converted;
    logic out_of_range_reg;
    
    generate
       if (PROCESS_MODE) begin 

        always @(posedge clk_in) begin
            if (rst) begin
                data_converted   <= '0;
                out_of_range_reg <= 0;
            end
            else begin
                out_of_range_reg <= out_of_range;
                if (data_in == {1'b1, {(DATA_WIDTH-1){1'b0}}})
                    data_converted <= data_in;
                else
                    data_converted <= data_in[DATA_WIDTH-1] ?{1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)}:data_in;
            end
        end
     end else begin
        always @(posedge clk_in) begin
            if (rst) begin
                data_converted   <= '0;
                out_of_range_reg <= 0;
            end
            else begin
                out_of_range_reg <= out_of_range;
                data_converted   <= data_in;
            end
        end
     end
    endgenerate
         
    logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
    logic buffer_ready;

    logic [$clog2(PACK_FACTOR):0] cnt;
    
    generate
      if (PACK_FACTOR == 1) begin
        always @(posedge clk_in) begin
            if (rst) begin
                buffer       <= '0;
                buffer_ready <= 0;
            end
            else begin
                buffer_ready <= 0;
                if (!out_of_range_reg) begin
                    buffer       <= data_converted;
                    buffer_ready <= 1;
                end
            end
        end
      end  else begin
        always @(posedge clk_in) begin
            if (rst) begin
                buffer <= '0;
                cnt <= '0; //
                buffer_ready <= 0;
            end
            else begin
                buffer_ready <= 0;
                if (!out_of_range_reg) begin
                    buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
                    if (cnt == PACK_FACTOR-1) begin
                        cnt <= 0;
                        buffer_ready <= 1;
                        buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
                    end
                    else begin
                        cnt <= cnt + 1;
                    end
                end
            end
        end
      end
    endgenerate
    
//    always @(posedge clk_in) begin
//        if (rst) begin
//            buffer <= '0;
//            cnt <= '0; //
//            buffer_ready <= 0;
//        end
//        else begin
//            buffer_ready <= 0;
//            if (!out_of_range_reg) begin
//                buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
//                if (cnt == PACK_FACTOR-1) begin
//                    cnt <= 0;
//                    buffer_ready <= 1;
//                    buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
//                end
//                else begin
//                    cnt <= cnt + 1;
//                end
//            end
//        end
//    end
    
    assign m_axis_tdata = buffer;
    assign m_axis_tvalid = buffer_ready;
    
endmodule