module tb_controller_wrapper_axil #(
  parameter int unsigned ADDR_W             = 16,
  parameter int unsigned DATA_W             = 32,
  parameter int unsigned USER_W             = 1,

  parameter int unsigned DAC_DATA_WIDTH     = 12,

  parameter int unsigned AXI_ADDR_WIDTH     = 16,
  parameter int unsigned AXIS_ID_WIDTH      = 8,
  parameter int unsigned LEN_WIDTH          = 20,
  parameter int unsigned AXIS_USER_WIDTH    = 1,
  parameter int unsigned AXIS_DEST_WIDTH    = 8,
  parameter int unsigned TAG_WIDTH          = 8,

  parameter int unsigned READ_DESC_WIDTH    = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH,
  parameter int unsigned WRITE_DESC_WIDTH   = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,

  parameter int unsigned READ_STATUS_WIDTH  = TAG_WIDTH + 4,
  parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4,

  // ceil(width / 8), чтобы keep/strb не стали слишком узкими для нестандартных ширин типа 12/49/61.
  parameter int unsigned READ_DESC_KEEP_W     = (READ_DESC_WIDTH + 7) / 8,
  parameter int unsigned WRITE_DESC_KEEP_W    = (WRITE_DESC_WIDTH + 7) / 8,
  parameter int unsigned READ_STATUS_KEEP_W   = (READ_STATUS_WIDTH + 7) / 8,
  parameter int unsigned WRITE_STATUS_KEEP_W  = (WRITE_STATUS_WIDTH + 7) / 8
)(
  input  logic                 ctrl_clk,
  input  logic                 rst,

  input  logic [ADDR_W-1:0]   s_axil_awaddr,
  input  logic [2:0]          s_axil_awprot,
  input  logic                s_axil_awvalid,
  output logic                s_axil_awready,

  input  logic [DATA_W-1:0]   s_axil_wdata,
  input  logic [DATA_W/8-1:0] s_axil_wstrb,
  input  logic                s_axil_wvalid,
  output logic                s_axil_wready,

  output logic [1:0]          s_axil_bresp,
  output logic                s_axil_bvalid,
  input  logic                s_axil_bready,

  input  logic [ADDR_W-1:0]   s_axil_araddr,
  input  logic [2:0]          s_axil_arprot,
  input  logic                s_axil_arvalid,
  output logic                s_axil_arready,

  output logic [DATA_W-1:0]   s_axil_rdata,
  output logic [1:0]          s_axil_rresp,
  output logic                s_axil_rvalid,
  input  logic                s_axil_rready,

  // ---------------------------------------------------------------------------
  // Минимальный flat-view для DMA AXIS портов.
  // Наружу оставлены только tdata/tvalid/tready в старом стиле.
  // Все остальные AXIS поля внутри обёртки завязаны на безопасные значения.
  // ---------------------------------------------------------------------------

  // DUT master -> testbench: descriptor commands.
  output logic [READ_DESC_WIDTH-1:0]   desc_read_cmd_out,
  output logic                         valid_desc_read,
  input  logic                         ready_desc_read,

  output logic [WRITE_DESC_WIDTH-1:0]  desc_write_cmd_out,
  output logic                         valid_desc_write,
  input  logic                         ready_desc_write,

  // testbench -> DUT slave: status commands.
  input  logic [READ_STATUS_WIDTH-1:0] status_read_cmd_in,
  input  logic                         valid_status_read,
  output logic                         ready_status_read,

  input  logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in,
  input  logic                          valid_status_write,
  output logic                          ready_status_write
);

  logic rst_n;
  assign rst_n = ~rst;

  // Для минимального теста держим все clock domain-ы на одном clock.
  logic dac_clk_in;
  logic adc_clk_in;
  assign dac_clk_in = ctrl_clk;
  assign adc_clk_in = ctrl_clk;

  logic finish;
  assign finish = 1'b0;

  // ---------------------------------------------------------------------------
  // AXI-Lite flat -> axi4l_if
  // ---------------------------------------------------------------------------

  axi4l_if #(
    .ADDR_W(ADDR_W),
    .DATA_W(DATA_W),
    .USER_W(USER_W)
  ) axil_bus (
    .aclk(ctrl_clk),
    .aresetn(rst_n)
  );

  axi4l_flat_to_if #(
    .ADDR_W(ADDR_W),
    .DATA_W(DATA_W),
    .USER_W(USER_W)
  ) u_axil_flat_to_if (
    .s_axil_awaddr (s_axil_awaddr),
    .s_axil_awprot (s_axil_awprot),
    .s_axil_awvalid(s_axil_awvalid),
    .s_axil_awready(s_axil_awready),

    .s_axil_wdata  (s_axil_wdata),
    .s_axil_wstrb  (s_axil_wstrb),
    .s_axil_wvalid (s_axil_wvalid),
    .s_axil_wready (s_axil_wready),

    .s_axil_bresp  (s_axil_bresp),
    .s_axil_bvalid (s_axil_bvalid),
    .s_axil_bready (s_axil_bready),

    .s_axil_araddr (s_axil_araddr),
    .s_axil_arprot (s_axil_arprot),
    .s_axil_arvalid(s_axil_arvalid),
    .s_axil_arready(s_axil_arready),

    .s_axil_rdata  (s_axil_rdata),
    .s_axil_rresp  (s_axil_rresp),
    .s_axil_rvalid (s_axil_rvalid),
    .s_axil_rready (s_axil_rready),

    .m_axil(axil_bus)
  );

  // ---------------------------------------------------------------------------
  // AXIS interfaces for the updated controller_wrapper_axil
  // ---------------------------------------------------------------------------

  axis_if #(
    .DATA_W(READ_STATUS_WIDTH),
    .KEEP_W(READ_STATUS_KEEP_W),
    .ID_W(AXIS_ID_WIDTH),
    .DEST_W(AXIS_DEST_WIDTH),
    .USER_W(AXIS_USER_WIDTH)
  ) axis_status_read (
    .aclk(ctrl_clk),
    .aresetn(rst_n)
  );

  axis_if #(
    .DATA_W(WRITE_STATUS_WIDTH),
    .KEEP_W(WRITE_STATUS_KEEP_W),
    .ID_W(AXIS_ID_WIDTH),
    .DEST_W(AXIS_DEST_WIDTH),
    .USER_W(AXIS_USER_WIDTH)
  ) axis_status_write (
    .aclk(ctrl_clk),
    .aresetn(rst_n)
  );

  axis_if #(
    .DATA_W(READ_DESC_WIDTH),
    .KEEP_W(READ_DESC_KEEP_W),
    .ID_W(AXIS_ID_WIDTH),
    .DEST_W(AXIS_DEST_WIDTH),
    .USER_W(AXIS_USER_WIDTH)
  ) axis_desc_read (
    .aclk(ctrl_clk),
    .aresetn(rst_n)
  );

  axis_if #(
    .DATA_W(WRITE_DESC_WIDTH),
    .KEEP_W(WRITE_DESC_KEEP_W),
    .ID_W(AXIS_ID_WIDTH),
    .DEST_W(AXIS_DEST_WIDTH),
    .USER_W(AXIS_USER_WIDTH)
  ) axis_desc_write (
    .aclk(ctrl_clk),
    .aresetn(rst_n)
  );

  // testbench flat status -> DUT AXIS slave ports
  axis_flat_to_if #(
    .DATA_W(READ_STATUS_WIDTH),
    .KEEP_W(READ_STATUS_KEEP_W),
    .ID_W(AXIS_ID_WIDTH),
    .DEST_W(AXIS_DEST_WIDTH),
    .USER_W(AXIS_USER_WIDTH)
  ) u_status_read_flat_to_if (
    .s_axis_tdata (status_read_cmd_in),
    .s_axis_tkeep ({READ_STATUS_KEEP_W{1'b1}}),
    .s_axis_tstrb ({READ_STATUS_KEEP_W{1'b1}}),
    .s_axis_tlast (1'b1),
    .s_axis_tid   ('0),
    .s_axis_tdest ('0),
    .s_axis_tuser ('0),
    .s_axis_tvalid(valid_status_read),
    .s_axis_tready(ready_status_read),

    .m_axis(axis_status_read)
  );

  axis_flat_to_if #(
    .DATA_W(WRITE_STATUS_WIDTH),
    .KEEP_W(WRITE_STATUS_KEEP_W),
    .ID_W(AXIS_ID_WIDTH),
    .DEST_W(AXIS_DEST_WIDTH),
    .USER_W(AXIS_USER_WIDTH)
  ) u_status_write_flat_to_if (
    .s_axis_tdata (status_write_cmd_in),
    .s_axis_tkeep ({WRITE_STATUS_KEEP_W{1'b1}}),
    .s_axis_tstrb ({WRITE_STATUS_KEEP_W{1'b1}}),
    .s_axis_tlast (1'b1),
    .s_axis_tid   ('0),
    .s_axis_tdest ('0),
    .s_axis_tuser ('0),
    .s_axis_tvalid(valid_status_write),
    .s_axis_tready(ready_status_write),

    .m_axis(axis_status_write)
  );

  // DUT AXIS master ports -> testbench flat descriptor outputs
  logic [READ_DESC_KEEP_W-1:0]     unused_desc_read_tkeep;
  logic [READ_DESC_KEEP_W-1:0]     unused_desc_read_tstrb;
  logic                            unused_desc_read_tlast;
  logic [AXIS_ID_WIDTH-1:0]        unused_desc_read_tid;
  logic [AXIS_DEST_WIDTH-1:0]      unused_desc_read_tdest;
  logic [AXIS_USER_WIDTH-1:0]      unused_desc_read_tuser;

  axis_if_to_flat #(
    .DATA_W(READ_DESC_WIDTH),
    .KEEP_W(READ_DESC_KEEP_W),
    .ID_W(AXIS_ID_WIDTH),
    .DEST_W(AXIS_DEST_WIDTH),
    .USER_W(AXIS_USER_WIDTH)
  ) u_desc_read_if_to_flat (
    .s_axis(axis_desc_read),

    .m_axis_tdata (desc_read_cmd_out),
    .m_axis_tkeep (unused_desc_read_tkeep),
    .m_axis_tstrb (unused_desc_read_tstrb),
    .m_axis_tlast (unused_desc_read_tlast),
    .m_axis_tid   (unused_desc_read_tid),
    .m_axis_tdest (unused_desc_read_tdest),
    .m_axis_tuser (unused_desc_read_tuser),
    .m_axis_tvalid(valid_desc_read),
    .m_axis_tready(ready_desc_read)
  );

  logic [WRITE_DESC_KEEP_W-1:0]    unused_desc_write_tkeep;
  logic [WRITE_DESC_KEEP_W-1:0]    unused_desc_write_tstrb;
  logic                            unused_desc_write_tlast;
  logic [AXIS_ID_WIDTH-1:0]        unused_desc_write_tid;
  logic [AXIS_DEST_WIDTH-1:0]      unused_desc_write_tdest;
  logic [AXIS_USER_WIDTH-1:0]      unused_desc_write_tuser;

  axis_if_to_flat #(
    .DATA_W(WRITE_DESC_WIDTH),
    .KEEP_W(WRITE_DESC_KEEP_W),
    .ID_W(AXIS_ID_WIDTH),
    .DEST_W(AXIS_DEST_WIDTH),
    .USER_W(AXIS_USER_WIDTH)
  ) u_desc_write_if_to_flat (
    .s_axis(axis_desc_write),

    .m_axis_tdata (desc_write_cmd_out),
    .m_axis_tkeep (unused_desc_write_tkeep),
    .m_axis_tstrb (unused_desc_write_tstrb),
    .m_axis_tlast (unused_desc_write_tlast),
    .m_axis_tid   (unused_desc_write_tid),
    .m_axis_tdest (unused_desc_write_tdest),
    .m_axis_tuser (unused_desc_write_tuser),
    .m_axis_tvalid(valid_desc_write),
    .m_axis_tready(ready_desc_write)
  );

  // Controller ADC/DAC outputs.
  logic [31:0]               adc_window_size;
  logic [31:0]               dac_pulse_width;
  logic [31:0]               dac_pulse_period;
  logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
  logic [15:0]               dac_pulse_num;
  logic [31:0]               adc_pulse_period;
  logic [15:0]               adc_pulse_num;
  logic                      dac_start;
  logic                      adc_start;
  logic                      dac_rst;
  logic                      adc_rst;

  controller_wrapper_axil #(
    .ADDR_W(ADDR_W),
    .DATA_W(DATA_W),
    .USER_W(USER_W),
    .DAC_DATA_WIDTH(DAC_DATA_WIDTH),
    .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
    .AXIS_ID_WIDTH(AXIS_ID_WIDTH),
    .LEN_WIDTH(LEN_WIDTH),
    .AXIS_USER_WIDTH(AXIS_USER_WIDTH),
    .AXIS_DEST_WIDTH(AXIS_DEST_WIDTH),
    .TAG_WIDTH(TAG_WIDTH),
    .READ_DESC_WIDTH(READ_DESC_WIDTH),
    .WRITE_DESC_WIDTH(WRITE_DESC_WIDTH),
    .READ_STATUS_WIDTH(READ_STATUS_WIDTH),
    .WRITE_STATUS_WIDTH(WRITE_STATUS_WIDTH)
  ) dut (
    .ctrl_clk(ctrl_clk),
    .dac_clk_in(dac_clk_in),
    .adc_clk_in(adc_clk_in),
    .rst_n(rst_n),
    .s_axil(axil_bus),

    .finish(finish),
    .adc_window_size(adc_window_size),

    .dac_pulse_width(dac_pulse_width),
    .dac_pulse_period(dac_pulse_period),
    .dac_pulse_height(dac_pulse_height),
    .dac_pulse_num(dac_pulse_num),

    .adc_pulse_period(adc_pulse_period),
    .adc_pulse_num(adc_pulse_num),

    .dac_start(dac_start),
    .adc_start(adc_start),
    .dac_rst(dac_rst),
    .adc_rst(adc_rst),

    .s_axis_status_read(axis_status_read),
    .s_axis_status_write(axis_status_write),

    .m_axis_desc_read(axis_desc_read),
    .m_axis_desc_write(axis_desc_write)
  );

endmodule : tb_controller_wrapper_axil