`timescale 1ns / 1ps


module generator
#(
    parameter DATA_WIDTH = 14,
    parameter ZERO_LEVEL = 8192 // 8192 or 0
    )
(
    input clk_in,
    input rst,
    input start,
    input [31:0]           pulse_width,
    input [31:0]           pulse_period,
    input [DATA_WIDTH-1:0] pulse_height,
    input [15:0]           pulse_num,
    input sample_done,
    
    output pulse,
    output[DATA_WIDTH-1:0] pulse_height_out,
    output logic sample_req
    
    );
    
  (* MARK_DEBUG="true" *)  logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
    
  (* MARK_DEBUG="true" *)  logic [31:0] pulse_width_reg, pulse_period_reg;
  (* MARK_DEBUG="true" *)  logic [15:0] pulse_num_reg;
    
  (* MARK_DEBUG="true" *)  logic enable;
  (* MARK_DEBUG="true" *)  logic [15:0] cnt_pulse_num;
  (* MARK_DEBUG="true" *)  logic [31:0] cnt_period;

    
    always @(posedge clk_in) begin
        if (rst) begin
            pulse_height_reg <= ZERO_LEVEL;
            pulse_height_out_reg <= ZERO_LEVEL;
            pulse_width_reg <= '0;
            pulse_period_reg <= '0;
            pulse_num_reg <= '0;
            enable <= 0;
            cnt_pulse_num <= '0;
            cnt_period <= '0;
            sample_req <= 0;
        end 
        else begin
            if (start & !enable) begin
                enable <= 1'b1;
                cnt_pulse_num <= '0;
                cnt_period <= '0;

                sample_req <= 1;
                
                pulse_width_reg <= pulse_width;
                pulse_period_reg <= pulse_period;
                pulse_num_reg <= pulse_num;
                pulse_height_reg <= pulse_height;
            end 
            if (enable) begin

                if (!sample_req && (cnt_period == 0)) begin
                    pulse_height_out_reg <= ZERO_LEVEL;
                    if (sample_done) begin
                        sample_req <= 1'b0;
                    end
                    
                    if (!sample_done) begin
                        if (cnt_pulse_num == pulse_num_reg - 1) begin
                            enable <= 1'b0;
                        end
                        else begin
                            cnt_pulse_num <= cnt_pulse_num + 1;
                            sample_req <= 1'b1;
                            cnt_period <= 1;
                        end
                    end
                end
                 else begin
                        
                    if (cnt_period < pulse_width_reg - 1) begin
                        pulse_height_out_reg <= pulse_height_reg;
                    end else begin
                        pulse_height_out_reg <= ZERO_LEVEL;
                    end
                    if (cnt_period == pulse_period_reg - 1) begin
                        cnt_period <= 0;
                    end else begin
                        cnt_period <= cnt_period + 1;
                    end
                    if (sample_req && sample_done) begin
                        sample_req <= 0;
                    end
                end
            end
        end
    end

     OBUF OBUF_pulse_clk (
        .I(clk_in),
        .O(pulse)
    );
    
    assign pulse_height_out = pulse_height_out_reg;
    
endmodule