`timescale 1ns / 1ps



module sampler
#(
    parameter DATA_WIDTH = 12,
    parameter PACK_FACTOR = 1,
    parameter PROCESS_MODE = 0
    )
(
    input clk_in,
    input rst,
    input [DATA_WIDTH-1:0] data_in,
    input out_of_range,
    input [31:0] smp_num,
    input sample_req,

    output logic [DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata,
    output logic                              m_axis_tvalid,
    output logic sample_done
    );
   (* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
   (* MARK_DEBUG="true" *) logic out_of_range_reg;
    (* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
   (* MARK_DEBUG="true" *) logic enable;
    
    generate
       if (PROCESS_MODE) begin 

        always @(posedge clk_in) begin
            if (rst) begin
                data_converted   <= '0;
                out_of_range_reg <= 0;
            end
            else begin
                out_of_range_reg <= out_of_range;
                if (data_in == {1'b1, {(DATA_WIDTH-1){1'b0}}})
                    data_converted <= data_in;
                else
                    data_converted <= data_in[DATA_WIDTH-1] ?{1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)}:data_in;
            end
        end
     end else begin
        always @(posedge clk_in) begin
            if (rst) begin
                data_converted   <= '0;
                out_of_range_reg <= 0;
            end
            else begin
                out_of_range_reg <= out_of_range;
                data_converted   <= data_in;
            end
        end
     end
    endgenerate
         
  (* MARK_DEBUG="true" *)  logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
  (* MARK_DEBUG="true" *)  logic buffer_ready;

    logic [$clog2(PACK_FACTOR):0] cnt;
    
    generate
      if (PACK_FACTOR == 1) begin
        always @(posedge clk_in) begin
            if (rst) begin
                buffer       <= '0;
                buffer_ready <= 0;
                cnt_smp_num <= '0;
                smp_num_reg <= '0;
                enable <= '0;
                sample_done <= 0;
            end
            else begin
                buffer_ready <= 0;
                if (sample_done && !sample_req) begin
                    sample_done <= 1'b0;
                end
                if (!enable && sample_req && !sample_done) begin
                    enable      <= 1;
                    cnt_smp_num <= 0;
                    smp_num_reg <= smp_num;
                end
                if (enable) begin
                    if (!out_of_range_reg) begin
                        if (cnt_smp_num != smp_num_reg) begin
                            buffer       <= data_converted;
                            buffer_ready <= 1;
                            cnt_smp_num <= cnt_smp_num +1;
                        end 
                        else begin
                            cnt_smp_num <= '0;
                            sample_done <= 1'b1;
                            buffer_ready <= 0;
                            buffer <= '0;
                            enable <= 0;
                        end
                    end
                end
            end
        end
      end  else begin
        always @(posedge clk_in) begin
            if (rst) begin
                buffer <= '0;
                cnt <= '0; //
                buffer_ready <= 0;
                cnt_smp_num <= '0;
                smp_num_reg <= '0;
                enable <= 0;
                sample_done <= 0;
            end
            else begin
                buffer_ready <= 0;
                if (sample_done && !sample_req) begin
                    sample_done <= 1'b0;
                end
                if (!enable && sample_req && !sample_done) begin
                    enable      <= 1;
                    cnt_smp_num <= 0;
                    smp_num_reg <= smp_num;
                end
                if (enable) begin
                    if (!out_of_range_reg) begin
                        if (cnt_smp_num != smp_num_reg) begin
                            cnt_smp_num <= cnt_smp_num +1;
                            buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
                            if (cnt == PACK_FACTOR-1) begin
                                cnt <= 0;
                                buffer_ready <= 1;
                                buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
                            end
                            else begin
                                cnt <= cnt + 1;
                            end
                        end 
                        else begin
                            sample_done <= 1'b1;
                            cnt_smp_num <= '0;
                            buffer_ready <= 0;
                            buffer <= '0;
                            enable <= 0;
                        end
                    end
                end
            end
        end
      end
    endgenerate
    
    assign m_axis_tdata = buffer;
    assign m_axis_tvalid = buffer_ready;
    
endmodule