rtl/accum/tests/Makefile

@@ -8,7 +8,7 @@
 
 # FPGA settings
 FPGA_PART = xc7a35tfgg484-1
-FPGA_TOP = control
+FPGA_TOP = accum
 FPGA_ARCH = artix7
 
 RTL_DIR = ../src
@@ -21,10 +21,10 @@ SYN_FILES += $(sort $(shell find ../src -type f \( -name '*.v' -o -name '*.sv' \
 XCI_FILES = $(sort $(shell find ../src -type f -name '*.xci'))
 
 XDC_FILES += ../../../constraints/ax7a035b.xdc
-# XDC_FILES += test_timing.xdc
+XDC_FILES += test_timing.xdc
 
-# SYN_FILES += controller_tb.sv
-# SIM_TOP = control_tb
+SYN_FILES += out_axis_fifo_tb.sv
+SIM_TOP = control_tb
 
 
 program: $(PROJECT).bit