dev/controller #5
377
rtl/controller/tests/controller_tb.sv
Normal file
377
rtl/controller/tests/controller_tb.sv
Normal file
@ -0,0 +1,377 @@
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`timescale 1ns/1ps
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module tb_control;
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localparam int unsigned DAC_DATA_WIDTH = 12;
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// Clocks / reset
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logic eth_clk_in;
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logic dac_clk_in;
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logic adc_clk_in;
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logic rst_n;
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// axi stream (input)
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logic [7:0] s_axis_tdata;
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logic s_axis_tvalid;
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logic s_axis_tready;
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logic s_axis_tlast;
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// ADC side input
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logic finish;
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// DUT outputs
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logic [31:0] dac_pulse_width;
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logic [31:0] dac_pulse_period;
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logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
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logic [15:0] dac_pulse_num;
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logic [31:0] adc_pulse_period;
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logic [15:0] adc_pulse_num;
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logic dac_start;
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logic adc_start;
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logic dac_rst;
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logic adc_rst;
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// DUT
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control #(
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
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) dut (
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.eth_clk_in (eth_clk_in),
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.dac_clk_in (dac_clk_in),
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.adc_clk_in (adc_clk_in),
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.rst_n (rst_n),
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.s_axis_tdata (s_axis_tdata),
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.s_axis_tvalid (s_axis_tvalid),
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.s_axis_tready (s_axis_tready),
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.s_axis_tlast (s_axis_tlast),
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.finish (finish),
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.dac_pulse_width (dac_pulse_width),
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.dac_pulse_period (dac_pulse_period),
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.dac_pulse_height (dac_pulse_height),
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.dac_pulse_num (dac_pulse_num),
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.adc_pulse_period (adc_pulse_period),
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.adc_pulse_num (adc_pulse_num),
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.dac_start (dac_start),
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.adc_start (adc_start),
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.dac_rst (dac_rst),
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.adc_rst (adc_rst)
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);
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// Clock generation
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initial begin
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eth_clk_in = 1'b0;
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forever #(1 * 4.000) eth_clk_in = ~eth_clk_in; // 125 MHz
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end
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initial begin
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dac_clk_in = 1'b0;
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forever #(1 * 3.846153846) dac_clk_in = ~dac_clk_in; // ~130 MHz
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end
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initial begin
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adc_clk_in = 1'b0;
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forever #(1 * 7.692307692) adc_clk_in = ~adc_clk_in; // ~65 MHz
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end
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// pulse counters and monitors for testing
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int dac_rst_count;
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int adc_rst_count;
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int dac_start_count;
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int adc_start_count;
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always_ff @(posedge dac_clk_in) begin
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if (!rst_n) begin
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dac_rst_count <= 0;
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dac_start_count <= 0;
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end else begin
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if (dac_rst) dac_rst_count <= dac_rst_count + 1;
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if (dac_start) dac_start_count <= dac_start_count + 1;
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end
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end
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always_ff @(posedge adc_clk_in) begin
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if (!rst_n) begin
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adc_rst_count <= 0;
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adc_start_count <= 0;
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end else begin
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if (adc_rst) adc_rst_count <= adc_rst_count + 1;
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if (adc_start) adc_start_count <= adc_start_count + 1;
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end
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end
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// some helpers for axi
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task automatic axis_send_byte(input logic [7:0] data, input logic last);
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begin
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@(negedge eth_clk_in);
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s_axis_tdata <= data;
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s_axis_tvalid <= 1'b1;
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s_axis_tlast <= last;
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@(posedge eth_clk_in);
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while (!s_axis_tready) begin
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@(posedge eth_clk_in);
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end
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s_axis_tvalid <= 1'b0;
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s_axis_tlast <= 1'b0;
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s_axis_tdata <= '0;
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end
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endtask
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task automatic send_cmd(input logic [7:0] cmd);
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begin
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axis_send_byte(cmd, 1'b1);
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end
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endtask
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task automatic send_set_data(
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input logic [31:0] pulse_width,
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input logic [31:0] pulse_period,
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input logic [15:0] pulse_num,
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input logic [15:0] pulse_height_raw
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);
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logic [95:0] payload;
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int i;
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begin
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// little-endian payload layout:
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// [31:0] pulse_width
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// [63:32] pulse_period
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// [79:64] pulse_num
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// [95:80] pulse_height_raw
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payload = {pulse_height_raw, pulse_num, pulse_period, pulse_width};
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axis_send_byte(8'h88, 1'b0); // CMD_SET_DATA
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for (i = 0; i < 12; i++) begin
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axis_send_byte(payload[i*8 +: 8], (i == 11));
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end
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end
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endtask
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task automatic pulse_finish;
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begin
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@(posedge adc_clk_in);
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finish <= 1'b1;
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@(posedge adc_clk_in);
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finish <= 1'b0;
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end
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endtask
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// waiters
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task automatic wait_dac_rst_count(input int expected, input int max_cycles = 100);
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int i;
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begin
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for (i = 0; i < max_cycles; i++) begin
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@(posedge dac_clk_in);
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if (dac_rst_count >= expected) return;
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end
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$fatal(1, "Timeout waiting for dac_rst_count >= %0d, current=%0d", expected, dac_rst_count);
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end
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endtask
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task automatic wait_adc_rst_count(input int expected, input int max_cycles = 100);
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int i;
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begin
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for (i = 0; i < max_cycles; i++) begin
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@(posedge adc_clk_in);
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if (adc_rst_count >= expected) return;
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end
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$fatal(1, "Timeout waiting for adc_rst_count >= %0d, current=%0d", expected, adc_rst_count);
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end
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endtask
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task automatic wait_dac_start_count(input int expected, input int max_cycles = 100);
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int i;
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begin
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for (i = 0; i < max_cycles; i++) begin
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@(posedge dac_clk_in);
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if (dac_start_count >= expected) return;
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end
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$fatal(1, "Timeout waiting for dac_start_count >= %0d, current=%0d", expected, dac_start_count);
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end
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endtask
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task automatic wait_adc_start_count(input int expected, input int max_cycles = 100);
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int i;
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begin
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for (i = 0; i < max_cycles; i++) begin
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@(posedge adc_clk_in);
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if (adc_start_count >= expected) return;
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end
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$fatal(1, "Timeout waiting for adc_start_count >= %0d, current=%0d", expected, adc_start_count);
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end
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endtask
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task automatic wait_cfg_applied(
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input logic [31:0] exp_pulse_width,
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input logic [31:0] exp_pulse_period,
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input logic [15:0] exp_pulse_num,
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input logic [15:0] exp_pulse_height_raw,
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input int max_cycles = 200
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);
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logic [DAC_DATA_WIDTH-1:0] exp_dac_height;
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int i;
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begin
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exp_dac_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0];
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for (i = 0; i < max_cycles; i++) begin
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@(posedge eth_clk_in);
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if ((dac_pulse_width === exp_pulse_width ) &&
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(dac_pulse_period === exp_pulse_period) &&
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(dac_pulse_num === exp_pulse_num ) &&
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(dac_pulse_height === exp_dac_height ) &&
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(adc_pulse_period === exp_pulse_period) &&
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(adc_pulse_num === exp_pulse_num )) begin
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return;
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end
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end
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$fatal(1,
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"Timeout waiting config outputs. Got: dac_width=%h dac_period=%h dac_num=%h dac_height=%h adc_period=%h adc_num=%h",
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dac_pulse_width, dac_pulse_period, dac_pulse_num, dac_pulse_height,
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adc_pulse_period, adc_pulse_num
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);
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end
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endtask
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// Test sequence
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logic [31:0] test_pulse_width;
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logic [31:0] test_pulse_period;
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logic [15:0] test_pulse_num;
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logic [15:0] test_pulse_height_raw;
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initial begin
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// defaults
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rst_n = 1'b0;
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s_axis_tdata = '0;
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s_axis_tvalid = 1'b0;
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s_axis_tlast = 1'b0;
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finish = 1'b0;
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test_pulse_width = 32'h11223344;
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test_pulse_period = 32'h55667788;
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test_pulse_num = 16'hA1B2;
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test_pulse_height_raw = 16'h0CDE; // for DAC_DATA_WIDTH=12 => 12'hCDE
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repeat (10) @(posedge eth_clk_in);
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rst_n = 1'b1;
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repeat (10) @(posedge eth_clk_in);
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$display("[%0t] TEST 1: soft_reset", $time);
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send_cmd(8'h0F);
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wait_dac_rst_count(1);
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wait_adc_rst_count(1);
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if (dac_rst_count != 1) begin
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$fatal(1, "Expected exactly one dac_rst pulse after first soft_reset, got %0d", dac_rst_count);
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end
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if (adc_rst_count != 1) begin
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$fatal(1, "Expected exactly one adc_rst pulse after first soft_reset, got %0d", adc_rst_count);
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end
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$display("[%0t] TEST 1 passed", $time);
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$display("[%0t] TEST 2: set_data", $time);
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send_set_data(
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test_pulse_width,
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test_pulse_period,
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test_pulse_num,
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test_pulse_height_raw
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);
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wait_cfg_applied(
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test_pulse_width,
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test_pulse_period,
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test_pulse_num,
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test_pulse_height_raw
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);
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if (dac_pulse_width !== 32'h11223344) begin
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$fatal(1, "dac_pulse_width mismatch: got %h expected %h", dac_pulse_width, 32'h11223344);
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end
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if (dac_pulse_period !== 32'h55667788) begin
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$fatal(1, "dac_pulse_period mismatch: got %h expected %h", dac_pulse_period, 32'h55667788);
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end
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if (dac_pulse_num !== 16'hA1B2) begin
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$fatal(1, "dac_pulse_num mismatch: got %h expected %h", dac_pulse_num, 16'hA1B2);
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end
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if (dac_pulse_height !== 12'hCDE) begin
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$fatal(1, "dac_pulse_height mismatch: got %h expected %h", dac_pulse_height, 12'hCDE);
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end
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if (adc_pulse_period !== 32'h55667788) begin
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$fatal(1, "adc_pulse_period mismatch: got %h expected %h", adc_pulse_period, 32'h55667788);
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end
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if (adc_pulse_num !== 16'hA1B2) begin
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$fatal(1, "adc_pulse_num mismatch: got %h expected %h", adc_pulse_num, 16'hA1B2);
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end
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$display("[%0t] TEST 2 passed", $time);
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repeat (20) @(posedge eth_clk_in);
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$display("[%0t] TEST 3: start", $time);
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send_cmd(8'hF0);
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wait_dac_start_count(1);
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wait_adc_start_count(1);
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if (dac_start_count != 1) begin
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$fatal(1, "Expected exactly one dac_start pulse after first start, got %0d", dac_start_count);
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end
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if (adc_start_count != 1) begin
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$fatal(1, "Expected exactly one adc_start pulse after first start, got %0d", adc_start_count);
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end
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$display("[%0t] TEST 3 start pulses passed", $time);
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// release busy by finish pulse from ADC domain
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$display("[%0t] Sending finish pulse", $time);
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pulse_finish();
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// a bit of wait for finish CDC back to ETH
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repeat (20) @(posedge eth_clk_in);
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// sanity check that commands are accepted again after finish
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$display("[%0t] TEST 4: soft_reset after finish", $time);
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send_cmd(8'h0F);
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wait_dac_rst_count(2);
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wait_adc_rst_count(2);
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if (dac_rst_count != 2) begin
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$fatal(1, "Expected exactly two dac_rst pulses total, got %0d", dac_rst_count);
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end
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if (adc_rst_count != 2) begin
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$fatal(1, "Expected exactly two adc_rst pulses total, got %0d", adc_rst_count);
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end
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$display("[%0t] TEST 4 passed", $time);
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$display("==============================================");
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$display("ALL BASIC TESTS PASSED");
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$display("dac_rst_count = %0d", dac_rst_count);
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$display("adc_rst_count = %0d", adc_rst_count);
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$display("dac_start_count = %0d", dac_start_count);
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$display("adc_start_count = %0d", adc_start_count);
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$display("==============================================");
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#100;
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$finish;
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end
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endmodule
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13
rtl/controller/tests/test_timing.xdc
Normal file
13
rtl/controller/tests/test_timing.xdc
Normal file
@ -0,0 +1,13 @@
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# Primary clocks
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create_clock -name eth_clk -period 8.000 [get_ports eth_clk_in]
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create_clock -name dac_clk -period 7.692 [get_ports dac_clk_in]
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create_clock -name adc_clk -period 15.385 [get_ports adc_clk_in]
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# Asynchronous clock groups
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# eth, dac, adc are independent domains
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set_clock_groups -name ASYNC_ETH_DAC_ADC -asynchronous \
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-group [get_clocks eth_clk] \
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-group [get_clocks dac_clk] \
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-group [get_clocks adc_clk]
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Reference in New Issue
Block a user