dev/controller #5
472
rtl/controller/src/controller.sv
Normal file
472
rtl/controller/src/controller.sv
Normal file
@ -0,0 +1,472 @@
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module control #(
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parameter int unsigned DAC_DATA_WIDTH = 12
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) (
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input logic eth_clk_in,
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input logic dac_clk_in,
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input logic adc_clk_in,
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input logic rst_n,
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// AXI stream slave, eth_clk_in domain
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input logic [7:0] s_axis_tdata,
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input logic s_axis_tvalid,
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output logic s_axis_tready,
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input logic s_axis_tlast,
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// adc_clk_in domain
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input logic finish,
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// dac_clk_in domain outputs
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output logic [31:0] dac_pulse_width,
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output logic [31:0] dac_pulse_period,
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output logic [DAC_DATA_WIDTH-1:0] dac_pulse_height,
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output logic [15:0] dac_pulse_num,
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// adc_clk_in domain outputs
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output logic [31:0] adc_pulse_period,
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output logic [15:0] adc_pulse_num,
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// pulse outputs
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output logic dac_start,
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output logic adc_start,
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output logic dac_rst,
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output logic adc_rst
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);
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// static checks
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initial begin
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if (DAC_DATA_WIDTH > 16) begin
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$error("DAC_DATA_WIDTH must be <= 16");
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end
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if (DAC_DATA_WIDTH == 0) begin
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$error("DAC_DATA_WIDTH must be > 0");
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end
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end
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// command constants
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localparam logic [7:0] CMD_SOFT_RESET = 8'h0F;
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localparam logic [7:0] CMD_START = 8'hF0;
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localparam logic [7:0] CMD_SET_DATA = 8'h88;
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// reset synchronizers: async assert, sync deassert in each domain
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logic eth_rst_ff1, eth_rst_ff2;
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logic dac_rst_ff1, dac_rst_ff2;
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logic adc_rst_ff1, adc_rst_ff2;
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logic eth_rst;
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logic dac_rst_int;
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logic adc_rst_int;
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always_ff @(posedge eth_clk_in or negedge rst_n) begin
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if (!rst_n) begin
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eth_rst_ff1 <= 1'b1;
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eth_rst_ff2 <= 1'b1;
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end else begin
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eth_rst_ff1 <= 1'b0;
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eth_rst_ff2 <= eth_rst_ff1;
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end
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end
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always_ff @(posedge dac_clk_in or negedge rst_n) begin
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if (!rst_n) begin
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dac_rst_ff1 <= 1'b1;
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dac_rst_ff2 <= 1'b1;
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end else begin
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dac_rst_ff1 <= 1'b0;
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dac_rst_ff2 <= dac_rst_ff1;
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end
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end
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always_ff @(posedge adc_clk_in or negedge rst_n) begin
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if (!rst_n) begin
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adc_rst_ff1 <= 1'b1;
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adc_rst_ff2 <= 1'b1;
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end else begin
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adc_rst_ff1 <= 1'b0;
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adc_rst_ff2 <= adc_rst_ff1;
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end
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end
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assign eth_rst = eth_rst_ff2;
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assign dac_rst_int = dac_rst_ff2;
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assign adc_rst_int = adc_rst_ff2;
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// axi stream is always accepted. If packet is not needed, it is discarded.
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assign s_axis_tready = 1'b1;
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wire axis_hs = s_axis_tvalid & s_axis_tready;
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// -------------------------------------------------------------------------
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// Shared 96-bit config bus in ETH domain
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//
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// Byte order for SET_DATA payload, little-endian:
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// payload byte 0 -> cfg_bus_eth[7:0]
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// payload byte 1 -> cfg_bus_eth[15:8]
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// ...etc...
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// payload byte 11 -> cfg_bus_eth[95:88]
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//
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// Field layout inside cfg_bus_eth:
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// [31:0] pulse_width
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// [63:32] pulse_period
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// [79:64] pulse_num
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// [95:80] pulse_height_raw[15:0]
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// -------------------------------------------------------------------------
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logic [95:0] cfg_bus_eth;
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logic [95:0] cfg_shift_eth;
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// ETH-domain parser and control
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typedef enum logic [2:0] {
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ST_IDLE = 3'd0,
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ST_RECV_CFG = 3'd1,
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ST_WAIT_CFG_ACK = 3'd2,
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ST_DISCARD = 3'd3
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} eth_state_t;
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eth_state_t eth_state;
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logic [3:0] cfg_byte_cnt;
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// Busy flag: set by START command, cleared by finish event from ADC domain
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logic busy_flag_eth;
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// Pending ACKs for config delivery
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logic cfg_wait_dac_ack;
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logic cfg_wait_adc_ack;
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// Event toggles ETH -> DAC/ADC
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logic start_toggle_eth;
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logic rst_toggle_eth;
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// Config request toggles ETH -> DAC/ADC
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logic cfg_req_toggle_dac_eth;
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logic cfg_req_toggle_adc_eth;
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// ACK toggles DAC/ADC -> ETH
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logic cfg_ack_toggle_dac;
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logic cfg_ack_toggle_adc;
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(* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_dac_meta, cfg_ack_toggle_dac_sync, cfg_ack_toggle_dac_sync_d;
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(* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_adc_meta, cfg_ack_toggle_adc_sync, cfg_ack_toggle_adc_sync_d;
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wire cfg_ack_pulse_dac_eth = cfg_ack_toggle_dac_sync ^ cfg_ack_toggle_dac_sync_d;
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wire cfg_ack_pulse_adc_eth = cfg_ack_toggle_adc_sync ^ cfg_ack_toggle_adc_sync_d;
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always_ff @(posedge eth_clk_in or posedge eth_rst) begin
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if (eth_rst) begin
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cfg_ack_toggle_dac_meta <= 1'b0;
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cfg_ack_toggle_dac_sync <= 1'b0;
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cfg_ack_toggle_dac_sync_d <= 1'b0;
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cfg_ack_toggle_adc_meta <= 1'b0;
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cfg_ack_toggle_adc_sync <= 1'b0;
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cfg_ack_toggle_adc_sync_d <= 1'b0;
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end else begin
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cfg_ack_toggle_dac_meta <= cfg_ack_toggle_dac;
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cfg_ack_toggle_dac_sync <= cfg_ack_toggle_dac_meta;
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cfg_ack_toggle_dac_sync_d <= cfg_ack_toggle_dac_sync;
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cfg_ack_toggle_adc_meta <= cfg_ack_toggle_adc;
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cfg_ack_toggle_adc_sync <= cfg_ack_toggle_adc_meta;
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cfg_ack_toggle_adc_sync_d <= cfg_ack_toggle_adc_sync;
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end
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end
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// finish event: ADC -> ETH via toggle CDC
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logic finish_toggle_adc;
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logic finish_meta_eth, finish_sync_eth, finish_sync_eth_d;
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wire finish_pulse_eth = finish_sync_eth ^ finish_sync_eth_d;
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always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
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if (adc_rst_int) begin
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finish_toggle_adc <= 1'b0;
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end else if (finish) begin
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finish_toggle_adc <= ~finish_toggle_adc;
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end
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end
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always_ff @(posedge eth_clk_in or posedge eth_rst) begin
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if (eth_rst) begin
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finish_meta_eth <= 1'b0;
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finish_sync_eth <= 1'b0;
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finish_sync_eth_d <= 1'b0;
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end else begin
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finish_meta_eth <= finish_toggle_adc;
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finish_sync_eth <= finish_meta_eth;
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finish_sync_eth_d <= finish_sync_eth;
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end
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end
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// ETH FSM
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always_ff @(posedge eth_clk_in or posedge eth_rst) begin
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if (eth_rst) begin
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eth_state <= ST_IDLE;
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cfg_byte_cnt <= '0;
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cfg_shift_eth <= '0;
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cfg_bus_eth <= '0;
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busy_flag_eth <= 1'b0;
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start_toggle_eth <= 1'b0;
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rst_toggle_eth <= 1'b0;
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cfg_req_toggle_dac_eth <= 1'b0;
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cfg_req_toggle_adc_eth <= 1'b0;
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cfg_wait_dac_ack <= 1'b0;
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cfg_wait_adc_ack <= 1'b0;
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end else begin
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// finish always clears busy
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if (finish_pulse_eth) begin
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busy_flag_eth <= 1'b0;
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end
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// config acks
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if (cfg_ack_pulse_dac_eth) begin
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cfg_wait_dac_ack <= 1'b0;
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end
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if (cfg_ack_pulse_adc_eth) begin
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cfg_wait_adc_ack <= 1'b0;
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end
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case (eth_state)
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ST_IDLE: begin
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cfg_byte_cnt <= '0;
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cfg_shift_eth <= cfg_shift_eth;
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if (axis_hs) begin
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// if busy, drop the whole packet
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if (busy_flag_eth) begin
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if (!s_axis_tlast) begin
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eth_state <= ST_DISCARD;
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end
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end else begin
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unique case (s_axis_tdata)
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CMD_SOFT_RESET: begin
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// command packet must be exactly 1 byte
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if (s_axis_tlast) begin
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rst_toggle_eth <= ~rst_toggle_eth;
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end else begin
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eth_state <= ST_DISCARD;
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end
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end
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CMD_START: begin
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// command packet must be exactly 1 byte
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if (s_axis_tlast) begin
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start_toggle_eth <= ~start_toggle_eth;
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busy_flag_eth <= 1'b1;
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end else begin
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eth_state <= ST_DISCARD;
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end
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end
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CMD_SET_DATA: begin
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// expect exactly 12 bytes after command
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if (s_axis_tlast) begin
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// no payload, invalid packet
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eth_state <= ST_IDLE;
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end else begin
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cfg_byte_cnt <= 4'd0;
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cfg_shift_eth <= '0;
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eth_state <= ST_RECV_CFG;
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end
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end
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default: begin
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// unknown command: discard packet remainder if any
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if (!s_axis_tlast) begin
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eth_state <= ST_DISCARD;
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end
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end
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endcase
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end
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end
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end
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ST_RECV_CFG: begin
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if (axis_hs) begin
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// little endian packing
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cfg_shift_eth[cfg_byte_cnt*8 +: 8] <= s_axis_tdata;
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if (cfg_byte_cnt == 4'd11) begin
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// this must be the final payload byte
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if (s_axis_tlast) begin
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cfg_bus_eth <= {s_axis_tdata, cfg_shift_eth[87:0]};
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cfg_req_toggle_dac_eth <= ~cfg_req_toggle_dac_eth;
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cfg_req_toggle_adc_eth <= ~cfg_req_toggle_adc_eth;
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cfg_wait_dac_ack <= 1'b1;
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cfg_wait_adc_ack <= 1'b1;
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eth_state <= ST_WAIT_CFG_ACK;
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end else begin
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// too many bytes in packet
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eth_state <= ST_DISCARD;
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end
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end else begin
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// early tlast means packet too short!!
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if (s_axis_tlast) begin
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eth_state <= ST_IDLE;
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end else begin
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cfg_byte_cnt <= cfg_byte_cnt + 4'd1;
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end
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end
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end
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end
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ST_WAIT_CFG_ACK: begin
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// any incoming packet while waiting ack is discarded
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if (cfg_ack_pulse_dac_eth || cfg_ack_pulse_adc_eth) begin
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if ((~cfg_wait_dac_ack || cfg_ack_pulse_dac_eth) &&
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(~cfg_wait_adc_ack || cfg_ack_pulse_adc_eth)) begin
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eth_state <= ST_IDLE;
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end
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end
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if (axis_hs && !s_axis_tlast) begin
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eth_state <= ST_DISCARD;
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end
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end
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ST_DISCARD: begin
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if (axis_hs && s_axis_tlast) begin
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eth_state <= ST_IDLE;
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end
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end
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default: begin
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eth_state <= ST_IDLE;
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end
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endcase
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end
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end
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// ETH -> DAC: start/reset event sync
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(* ASYNC_REG = "TRUE" *) logic start_meta_dac, start_sync_dac;
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logic start_sync_dac_d;
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(* ASYNC_REG = "TRUE" *) logic rst_meta_dac, rst_sync_dac;
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logic rst_sync_dac_d;
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wire dac_start_pulse = start_sync_dac ^ start_sync_dac_d;
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wire dac_rst_pulse = rst_sync_dac ^ rst_sync_dac_d;
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always_ff @(posedge dac_clk_in or posedge dac_rst_int) begin
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if (dac_rst_int) begin
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start_meta_dac <= 1'b0;
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start_sync_dac <= 1'b0;
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start_sync_dac_d <= 1'b0;
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rst_meta_dac <= 1'b0;
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rst_sync_dac <= 1'b0;
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rst_sync_dac_d <= 1'b0;
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dac_start <= 1'b0;
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dac_rst <= 1'b0;
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end else begin
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start_meta_dac <= start_toggle_eth;
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start_sync_dac <= start_meta_dac;
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start_sync_dac_d <= start_sync_dac;
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rst_meta_dac <= rst_toggle_eth;
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rst_sync_dac <= rst_meta_dac;
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rst_sync_dac_d <= rst_sync_dac;
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dac_start <= dac_start_pulse;
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dac_rst <= dac_rst_pulse;
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end
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end
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// ETH -> ADC: start/reset event sync
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(* ASYNC_REG = "TRUE" *) logic start_meta_adc, start_sync_adc;
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logic start_sync_adc_d;
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(* ASYNC_REG = "TRUE" *) logic rst_meta_adc, rst_sync_adc;
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logic rst_sync_adc_d;
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wire adc_start_pulse = start_sync_adc ^ start_sync_adc_d;
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wire adc_rst_pulse = rst_sync_adc ^ rst_sync_adc_d;
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always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
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if (adc_rst_int) begin
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start_meta_adc <= 1'b0;
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start_sync_adc <= 1'b0;
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start_sync_adc_d <= 1'b0;
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rst_meta_adc <= 1'b0;
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rst_sync_adc <= 1'b0;
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rst_sync_adc_d <= 1'b0;
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adc_start <= 1'b0;
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adc_rst <= 1'b0;
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end else begin
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start_meta_adc <= start_toggle_eth;
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start_sync_adc <= start_meta_adc;
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start_sync_adc_d <= start_sync_adc;
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rst_meta_adc <= rst_toggle_eth;
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rst_sync_adc <= rst_meta_adc;
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rst_sync_adc_d <= rst_sync_adc;
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adc_start <= adc_start_pulse;
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adc_rst <= adc_rst_pulse;
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end
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end
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// ETH -> DAC config CDC
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// cfg_bus_eth is kept stable in ETH domain until DAC and ADC both ACK.
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(* ASYNC_REG = "TRUE" *) logic cfg_req_meta_dac, cfg_req_sync_dac;
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logic cfg_req_sync_dac_d;
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wire cfg_req_pulse_dac = cfg_req_sync_dac ^ cfg_req_sync_dac_d;
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always_ff @(posedge dac_clk_in or posedge dac_rst_int) begin
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if (dac_rst_int) begin
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cfg_req_meta_dac <= 1'b0;
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cfg_req_sync_dac <= 1'b0;
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cfg_req_sync_dac_d<= 1'b0;
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cfg_ack_toggle_dac<= 1'b0;
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dac_pulse_width <= '0;
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dac_pulse_period <= '0;
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dac_pulse_num <= '0;
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dac_pulse_height <= '0;
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end else begin
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cfg_req_meta_dac <= cfg_req_toggle_dac_eth;
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cfg_req_sync_dac <= cfg_req_meta_dac;
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cfg_req_sync_dac_d <= cfg_req_sync_dac;
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if (cfg_req_pulse_dac) begin
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dac_pulse_width <= cfg_bus_eth[31:0];
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dac_pulse_period <= cfg_bus_eth[63:32];
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dac_pulse_num <= cfg_bus_eth[79:64];
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dac_pulse_height <= cfg_bus_eth[80 +: DAC_DATA_WIDTH];
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cfg_ack_toggle_dac <= ~cfg_ack_toggle_dac;
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end
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end
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end
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// ETH -> ADC config CDC
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logic cfg_req_meta_adc, cfg_req_sync_adc, cfg_req_sync_adc_d;
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wire cfg_req_pulse_adc = cfg_req_sync_adc ^ cfg_req_sync_adc_d;
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always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
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if (adc_rst_int) begin
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cfg_req_meta_adc <= 1'b0;
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cfg_req_sync_adc <= 1'b0;
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cfg_req_sync_adc_d <= 1'b0;
|
||||
cfg_ack_toggle_adc <= 1'b0;
|
||||
|
||||
adc_pulse_period <= '0;
|
||||
adc_pulse_num <= '0;
|
||||
end else begin
|
||||
cfg_req_meta_adc <= cfg_req_toggle_adc_eth;
|
||||
cfg_req_sync_adc <= cfg_req_meta_adc;
|
||||
cfg_req_sync_adc_d <= cfg_req_sync_adc;
|
||||
|
||||
if (cfg_req_pulse_adc) begin
|
||||
adc_pulse_period <= cfg_bus_eth[63:32];
|
||||
adc_pulse_num <= cfg_bus_eth[79:64];
|
||||
|
||||
cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user