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dev/ethernet #4

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baulin.fa merged 21 commits from dev/ethernet into master 2026-04-14 15:42:09 +03:00
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10
rtl/ethernet-udp/src/eth/mac/mac_top.v
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@ -1,8 +1,6 @@
//////////////////////////////////////////////////////////////////////////////////////
//Module Name : mac_top
//Description :
//
//////////////////////////////////////////////////////////////////////////////////////
// Top module for base ethernet operations
// inheireted from Alinx
`timescale 1 ns/1 ns
module mac_top
(
@ -37,6 +35,7 @@ module mac_top
input [10:0] udp_rec_ram_read_addr,
output [15:0] udp_rec_data_length,
output udp_rec_data_valid,
output [11:0] udp_ram_data_count,
output arp_found,
output mac_not_exist
@ -81,6 +80,7 @@ mac_tx_top mac_tx0
.arp_rec_source_ip_addr (arp_rec_source_ip_addr ),
.arp_rec_source_mac_addr (arp_rec_source_mac_addr ),
.arp_request_req (arp_request_req ),
.udp_ram_data_count (udp_ram_data_count ),
.ram_wr_data (ram_wr_data) ,

6
rtl/ethernet-udp/src/eth/mac/tx/mac_tx_top.v
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@ -31,8 +31,9 @@ module mac_tx_top
(* MARK_DEBUG="true" *)input [15:0] udp_send_data_length,
(* MARK_DEBUG="true" *)output udp_tx_end,
(* MARK_DEBUG="true" *)output almost_full,
(* MARK_DEBUG="true" *)output [11:0] udp_ram_data_count,
output upper_data_req,
(* MARK_DEBUG="true" *)output upper_data_req,
input icmp_tx_ready,
input [7:0] icmp_tx_data,
input icmp_tx_end,
@ -251,7 +252,8 @@ udp_tx udp0
.udp_tx_ready (udp_tx_ready ),
.udp_tx_data (udp_tx_data ),
.udp_tx_end (udp_tx_end ),
.almost_full (almost_full )
.almost_full (almost_full ),
.udp_ram_data_count (udp_ram_data_count )
) ;
endmodule

11
rtl/ethernet-udp/src/eth/mac/tx/udp_tx.v
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@ -27,13 +27,14 @@ module udp_tx
output reg udp_tx_ready,
output reg [7:0] udp_tx_data,
output reg udp_tx_end,
output almost_full
output almost_full,
output [11:0] udp_ram_data_count
) ;
reg ram_rd_en ;
wire [3:0] usedw ;
(* MARK_DEBUG="true" *) wire [3:0] usedw ;
reg [3:0] fifo_count ;
reg [7:0] ram_rdata_d0 ;
@ -62,7 +63,7 @@ parameter UDP_SEND = 6'b010000 ;
parameter UDP_END = 6'b100000 ;
reg [5:0] state ;
(* MARK_DEBUG="true" *) reg [5:0] state ;
reg [5:0] next_state ;
@ -222,7 +223,7 @@ udp_tx_data_fifo tx_data_fifo
.full ( ), // output wire full
.almost_full (almost_full ), // output wire almost_full
.empty ( ), // output wire empty
.data_count ( ) // output wire [11 : 0] data_count
.data_count (udp_ram_data_count ) // output wire [11 : 0] data_count
);
@ -356,7 +357,7 @@ udp_tx_data_fifo tx_data_fifo
localparam GEN_CHECKSUM_END = 6'b010000 ;
localparam CHECKSUM_WAIT = 6'b100000 ;
reg [5:0] ck_state ;
(* MARK_DEBUG="true" *) reg [5:0] ck_state ;
reg [5:0] ck_next_state ;
always @(posedge clk or negedge rst_n)