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add accum_done signal #16

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babintsev.lv merged 1 commits from dev/accum_rework into dev/design 2026-07-28 14:11:29 +03:00
Conversation 0 Commits 1 Files Changed 2
+6 -4
2 changed files with 6 additions and 4 deletions
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rtl/accum/src/accum.sv
+2 -2
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@@ -22,7 +22,8 @@ module accumulator
output out_valid, output out_valid,
output readout_begin, output readout_begin,
input batch_req, input batch_req,
input finish input finish,
output logic accum_done
); );
logic [31:0] smp_num_reg, cnt_smp_num; logic [31:0] smp_num_reg, cnt_smp_num;
@@ -66,7 +67,6 @@ module accumulator
// Then the next sequence can read the same address it is written // Then the next sequence can read the same address it is written
logic accum_pipe_bypass_valid; logic accum_pipe_bypass_valid;
logic [ACCUM_WIDTH-1:0] accum_pipe_bypass_data; logic [ACCUM_WIDTH-1:0] accum_pipe_bypass_data;
logic accum_done;
logic accum_accept_last; logic accum_accept_last;
logic accum_accept_last_all; logic accum_accept_last_all;
rtl/accum/src/accum_top.sv
+4 -2
View File
@@ -34,7 +34,8 @@ module accumulator_top
input logic m_axis_tready, input logic m_axis_tready,
output logic m_axis_tlast, output logic m_axis_tlast,
output logic finish output logic finish,
output logic accum_done
); );
wire [ACCUM_WIDTH-1:0] out_data; wire [ACCUM_WIDTH-1:0] out_data;
@@ -91,7 +92,8 @@ module accumulator_top
.out_valid(out_valid), .out_valid(out_valid),
.readout_begin(readout_begin), .readout_begin(readout_begin),
.batch_req(batch_req), .batch_req(batch_req),
.finish(finish_int) .finish(finish_int),
.accum_done(accum_done)
); );
out_axis_fifo #( out_axis_fifo #(