rtl: sampler ready

rtl/generator/src/generator.sv

@@ -1,99 +0,0 @@
-`timescale 1ns / 1ps
-
-
-module generator
-#(
-    parameter DATA_WIDTH = 14
-    )
-(
-    input clk_in,
-    input rst,
-    input start,
-    input [31:0]           pulse_width,
-    input [31:0]           pulse_period,
-    input [DATA_WIDTH-1:0] pulse_height,
-    input [15:0]           pulse_num,
-    
-    output pulse,
-    output[DATA_WIDTH-1:0] pulse_height_out
-    
-    );
-    
-    logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
-    logic pulse_reg;
-    
-    logic [31:0] pulse_width_reg, pulse_period_reg;
-    logic [15:0] pulse_num_reg;
-    
-    logic enable;
-    logic [15:0] cnt_pulse_num;
-    logic [31:0] cnt_period;
-    
-    logic start_d;
-
-    always @(posedge clk_in) begin
-        start_d <= start;
-    end
-
-    wire start_pulse = start & ~start_d;
-
-    
-    always @(posedge clk_in) begin
-        if (rst) begin
-            pulse_reg <= '0;
-            pulse_height_reg <= 0;
-            pulse_height_out_reg <= '0;
-            
-            pulse_width_reg <= '0;
-            pulse_period_reg <= '0;
-            pulse_num_reg <= '0;
-            enable <= 0;
-            cnt_pulse_num <= '0;
-            cnt_period <= '0;
-        end else begin
-            if (start) begin
-                enable <= 1'b1;
-//                pulse_width_reg <= pulse_width;
-//                pulse_period_reg <= pulse_period;
-//                pulse_num_reg <= pulse_num;
-//                pulse_height_reg <= pulse_height;
-                
-                cnt_pulse_num <= '0;
-                cnt_period <= '0;
-            end
-            if (enable) begin
-                pulse_reg <= 1;
-                
-                pulse_width_reg <= pulse_width;
-                pulse_period_reg <= pulse_period;
-                pulse_num_reg <= pulse_num;
-                pulse_height_reg <= pulse_height;
-                
-                if (pulse_reg) begin
-                
-                if (cnt_period < pulse_width_reg) begin
-                    pulse_height_out_reg <= pulse_height_reg;
-                end else begin
-                    pulse_height_out_reg <= '0;
-                end
-                if (cnt_period == pulse_period_reg - 1) begin
-                    cnt_period <= 0;
-                    if (cnt_pulse_num == pulse_num_reg - 1) begin
-                        enable <= 0;
-                        pulse_reg <= 0;
-                    end else begin
-                        cnt_pulse_num <= cnt_pulse_num + 1;
-                    end
-                end else begin
-                    cnt_period <= cnt_period + 1;
-                end
-                
-                end
-            end
-        end
-    end
-    
-    assign pulse_height_out = pulse_height_out_reg;
-    assign pulse = pulse_reg;
-    
-endmodule

rtl/generator/tests/generator_tb.sv

@@ -1,105 +0,0 @@
-`timescale 1ns / 1ps
-
-module generator_tb;
-
-    parameter DATA_WIDTH = 14;
-    parameter CLK_PERIOD = 16;
-
-    logic clk;
-    logic rst;
-    logic start;
-
-    logic [31:0] pulse_width;
-    logic [31:0] pulse_period;
-    logic [DATA_WIDTH-1:0] pulse_height;
-    logic [15:0] pulse_num;
-
-    logic pulse;
-    logic [DATA_WIDTH-1:0] pulse_height_out;
-
-    // DUT
-    generator #(
-        .DATA_WIDTH(DATA_WIDTH)
-    ) dut (
-        .clk_in(clk),
-        .rst(rst),
-        .start(start),
-        .pulse_width(pulse_width),
-        .pulse_period(pulse_period),
-        .pulse_height(pulse_height),
-        .pulse_num(pulse_num),
-        .pulse(pulse),
-        .pulse_height_out(pulse_height_out)
-    );
-
-    // Clock
-    initial begin
-        clk = 0;
-        forever #(CLK_PERIOD/2) clk = ~clk;
-    end
-
-    initial begin
-        $display("\n=== GENERATOR TEST ===\n");
-
-        rst = 1;
-        start = 0;
-
-        pulse_width  = 0;
-        pulse_period = 0;
-        pulse_height = 0;
-        pulse_num    = 0;
-
-        repeat(5) @(posedge clk);
-        rst = 0;
-
-        // --- Test 1 ---
-        // 3 clk 1, 5 clk 0,  4 pulses
-       repeat(2) @(posedge clk);
-        pulse_width  = 3;
-        pulse_period = 8;
-        pulse_num    = 4;
-        pulse_height = 14'h3FF;
-        start = 1;
-
-       repeat(1) @(posedge clk);
-        start = 0;
-
-        repeat(50) @(posedge clk);
-
-        // --- Test 2 ---
-        $display("\n--- SECOND RUN ---\n");
-
-        @(posedge clk);
-        pulse_width  = 2;
-        pulse_period = 5;
-        pulse_num    = 3;
-        pulse_height = 14'h155;
-        start = 1;
-
-        @(posedge clk);
-        start = 0;
-
-        repeat(40) @(posedge clk);
-        
-         pulse_width  = 3;
-        pulse_period = 8;
-        pulse_num    = 4;
-        pulse_height = 14'h3FF;
-        start = 1;
-
-       repeat(1) @(posedge clk);
-        start = 0;
-
-        repeat(50) @(posedge clk);
-
-        $display("\n=== TEST FINISHED ===");
-        $finish;
-    end
-
-    // Display
-    always @(posedge clk) begin
-        $display("t=%0t | pulse=%0b | height=%h",
-                  $time, pulse, pulse_height_out);
-    end
-
-endmodule

rtl/sampler/src/sampler.sv

@@ -0,0 +1,72 @@
+`timescale 1ns / 1ps
+
+
+
+module sampler
+#(
+    parameter DATA_WIDTH = 12,
+    parameter PACK_FACTOR = 3,
+    parameter PROCESS_MODE = 1
+    )
+(
+    input clk_in,
+    input rst,
+    input [DATA_WIDTH-1:0] data_in,
+    input out_of_range,
+
+    output logic [DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata,
+    output logic                              m_axis_tvalid
+    );
+    logic [DATA_WIDTH-1:0] data_converted;
+    logic out_of_range_reg;
+
+    always @( posedge clk_in) begin
+        if (rst) begin
+            data_converted <= '0;
+        end else begin
+            out_of_range_reg <= out_of_range;
+            if (PROCESS_MODE) begin
+                if (data_in == 12'b100000000000) begin
+                    data_converted <= data_in;
+                end else begin
+                    data_converted <= data_in[DATA_WIDTH-1]  ? {1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)} : data_in; 
+                    
+                end
+            end else begin
+                data_converted <= data_in; 
+            end
+        end
+    end 
+    
+         
+    logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
+    logic buffer_ready;
+
+    logic [$clog2(PACK_FACTOR):0] cnt;
+    
+    always @(posedge clk_in) begin
+        if (rst) begin
+            buffer <= '0;
+            cnt <= -1; //
+            buffer_ready <= 0;
+        end
+        else begin
+            buffer_ready <= 0;
+            if (!out_of_range_reg) begin
+                buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
+                if (cnt == PACK_FACTOR-1) begin
+                    cnt <= 0;
+                    buffer_ready <= 1;
+                    buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
+                end
+                else begin
+                    cnt <= cnt + 1;
+                end
+            end
+        end
+    end
+    
+    assign m_axis_tdata = buffer;
+    assign m_axis_tvalid = buffer_ready;
+    
+endmodule

rtl/sampler/tests/sampler_tb_advanced.sv

@@ -0,0 +1,120 @@
+`timescale 1ns / 1ps
+
+module sampler_tb;
+
+    parameter DATA_WIDTH = 12;
+    parameter PACK_FACTOR = 3;
+    parameter PROCESS_MODE = 1;
+    parameter CLK_PERIOD = 15.3846;  // 65 MHz
+
+    logic clk;
+    logic rst;
+    logic [DATA_WIDTH-1:0] data_in;
+    logic out_of_range;
+    logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
+    logic m_axis_tvalid;
+
+    sampler #(
+        .DATA_WIDTH(DATA_WIDTH),
+        .PACK_FACTOR(PACK_FACTOR),
+        .PROCESS_MODE(PROCESS_MODE)
+    ) dut (
+        .clk_in(clk),
+        .rst(rst),
+        .data_in(data_in),
+        .out_of_range(out_of_range),
+        .m_axis_tdata(m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid)
+    );
+
+    initial begin
+        clk = 0;
+        forever #(CLK_PERIOD/2) clk = ~clk;
+    end
+
+    task send(input [DATA_WIDTH-1:0] word, input bit oor);
+        @(posedge clk);
+        data_in <= word;
+        out_of_range <= oor;
+        $display("Send: %h (%0d) OOR=%b", word, word, oor);
+    endtask
+
+    initial begin
+        $display("\n=== SAMPLER TEST (MODE=%0d) ===\n", PROCESS_MODE);
+        
+        // Reset
+        rst = 1;
+        out_of_range = 0;
+        data_in = 0;
+//        send(12'h001, 0);
+        repeat(5) @(posedge clk);
+        rst = 0;
+        send(12'h001, 0);
+        repeat(1) @(posedge clk);
+        
+        // 1. Positive
+        $display("\n--- Positive numbers ---");
+//        send(12'h001, 0);
+        send(12'h002, 0);
+        send(12'h003, 0);
+        
+        send(12'h004, 0);
+        send(12'h005, 0);
+        send(12'h806, 0);
+        
+        // 2. Negative
+        $display("\n--- Negative numbers ---");
+        send(12'hFFF, 0);  // -1
+        send(12'hFFE, 0);  // -2
+        send(12'hFFD, 0);  // -3
+        
+        send(12'h800, 0);  // -2048
+        send(12'h801, 0);  // -2047
+        send(12'h802, 0);  // -2046
+        
+        // 3. Boundary
+        $display("\n--- Boundary values ---");
+        send(12'h000, 0);  // 0
+        send(12'h001, 0);  // 1
+        send(12'h7FF, 0);  // 2047 (max positive)
+        
+        send(12'h7FE, 0);  // 2046
+        send(12'h800, 0);  // -2048 (min negative)
+        send(12'hFFF, 0);  // -1
+        
+        // 4. Out of range tests
+        $display("\n--- Out of range tests ---");
+        
+
+        send(12'h00A, 0);
+        send(12'h00B, 1);  // 
+        send(12'h00C, 0);
+        send(12'h00D, 0);
+        send(12'h00E, 0);
+        send(12'h00F, 0);  
+        
+        send(12'h010, 0);
+        send(12'h011, 0);
+        send(12'h012, 1);  // 
+        
+        send(12'h013, 0);
+        send(12'h014, 0);
+        send(12'h015, 0); 
+        
+        repeat(10) @(posedge clk);
+        $display("\n=== TEST FINISHED ===");
+        $finish;
+    end
+
+    // Results
+    always @(posedge clk) begin
+        if (m_axis_tvalid) begin
+            $display("\n>>> PACKET RECEIVED at %0t ns:", $time);
+            $display("    Full: %h", m_axis_tdata);
+            $display("    Word0: %h", m_axis_tdata[11:0]);
+            $display("    Word1: %h", m_axis_tdata[23:12]);
+            $display("    Word2: %h\n", m_axis_tdata[35:24]);
+        end
+    end
+
+endmodule

rtl/sampler/tests/sampler_tb_basic.sv

@@ -0,0 +1,67 @@
+`timescale 1ns / 1ps
+
+module sampler_tb;
+
+    parameter DATA_WIDTH = 12;
+    parameter PACK_FACTOR = 3;
+    parameter PROCESS_MODE = 0;
+    
+    parameter CLK_PERIOD = 15.3846; 
+
+    logic clk;
+    logic rst;
+    logic [DATA_WIDTH-1:0] data_in;
+    logic out_of_range;
+
+    logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
+    logic m_axis_tvalid;
+
+    // DUT
+    sampler #(
+        .DATA_WIDTH(DATA_WIDTH),
+        .PACK_FACTOR(PACK_FACTOR),
+        .PROCESS_MODE(PROCESS_MODE)
+    ) dut (
+        .clk_in(clk),
+        .rst(rst),
+        .data_in(data_in),
+        .out_of_range(out_of_range),
+        .m_axis_tdata(m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid)
+    );
+
+    // clock
+     initial begin
+        clk = 0;
+        forever #(CLK_PERIOD/2) clk = ~clk;
+    end
+
+    integer i;
+
+    initial begin
+        clk = 0;
+        rst = 1;
+        data_in = 0;
+        out_of_range = 0;
+
+        #20;
+        rst = 0;
+        repeat(5) @(posedge clk);
+
+        for (i = 1; i < 20; i++) begin
+            @(posedge clk);
+
+            data_in <= i;
+        end
+
+        #50;
+        $finish;
+    end
+
+    always @(posedge clk) begin
+        if (m_axis_tvalid) begin
+            $display("TIME=%0t PACKED DATA = %h", $time, m_axis_tdata);
+        end
+    end
+
+endmodule