Compare commits
2 Commits
c75443d170
...
100feb0ea1
| Author | SHA1 | Date | |
|---|---|---|---|
| 100feb0ea1 | |||
| 1310555b55 |
352
rtl/ethernet-udp/tests/eth_axis/ethernet_test_minimal.xdc
Normal file
352
rtl/ethernet-udp/tests/eth_axis/ethernet_test_minimal.xdc
Normal file
@ -0,0 +1,352 @@
|
|||||||
|
# constrains for minimal ethernet stack
|
||||||
|
|
||||||
|
create_clock -period 5.000 [get_ports sys_clk_p]
|
||||||
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
|
||||||
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
|
||||||
|
set_property PACKAGE_PIN R4 [get_ports sys_clk_p]
|
||||||
|
set_property PACKAGE_PIN T4 [get_ports sys_clk_n]
|
||||||
|
|
||||||
|
set_property PACKAGE_PIN F15 [get_ports rst_n]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
|
||||||
|
|
||||||
|
set_property PACKAGE_PIN L13 [get_ports {led[0]}]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
|
||||||
|
set_property PACKAGE_PIN M13 [get_ports {led[1]}]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
|
||||||
|
set_property PACKAGE_PIN K14 [get_ports {led[2]}]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
|
||||||
|
set_property PACKAGE_PIN K13 [get_ports {led[3]}]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
|
||||||
|
#########################ethernet######################
|
||||||
|
create_clock -period 8.000 [get_ports rgmii_rxc]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[*]}]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[*]}]
|
||||||
|
set_property SLEW FAST [get_ports {rgmii_txd[*]}]
|
||||||
|
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports e_mdc]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports e_mdio]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports e_reset]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxctl]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txc]
|
||||||
|
set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txctl]
|
||||||
|
set_property SLEW FAST [get_ports rgmii_txc]
|
||||||
|
set_property SLEW FAST [get_ports rgmii_txctl]
|
||||||
|
|
||||||
|
set_property PACKAGE_PIN P17 [get_ports {rgmii_rxd[3]}]
|
||||||
|
set_property PACKAGE_PIN U17 [get_ports {rgmii_rxd[2]}]
|
||||||
|
set_property PACKAGE_PIN U18 [get_ports {rgmii_rxd[1]}]
|
||||||
|
set_property PACKAGE_PIN P19 [get_ports {rgmii_rxd[0]}]
|
||||||
|
set_property PACKAGE_PIN R16 [get_ports {rgmii_txd[3]}]
|
||||||
|
set_property PACKAGE_PIN R17 [get_ports {rgmii_txd[2]}]
|
||||||
|
set_property PACKAGE_PIN P16 [get_ports {rgmii_txd[1]}]
|
||||||
|
set_property PACKAGE_PIN N14 [get_ports {rgmii_txd[0]}]
|
||||||
|
set_property PACKAGE_PIN N13 [get_ports e_mdc]
|
||||||
|
set_property PACKAGE_PIN P14 [get_ports e_mdio]
|
||||||
|
set_property PACKAGE_PIN R14 [get_ports e_reset]
|
||||||
|
set_property PACKAGE_PIN V18 [get_ports rgmii_rxc]
|
||||||
|
set_property PACKAGE_PIN R19 [get_ports rgmii_rxctl]
|
||||||
|
set_property PACKAGE_PIN P15 [get_ports rgmii_txc]
|
||||||
|
set_property PACKAGE_PIN N17 [get_ports rgmii_txctl]
|
||||||
|
|
||||||
|
|
||||||
|
connect_debug_port u_ila_0/probe0 [get_nets [list {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[0]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[1]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[2]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[3]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[4]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[5]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[6]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[7]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[8]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[9]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[10]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[11]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[12]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[13]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[14]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
|
||||||
|
connect_debug_port u_ila_0/probe1 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
|
||||||
|
connect_debug_port u_ila_0/probe2 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
|
||||||
|
connect_debug_port u_ila_0/probe3 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[10]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[11]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[12]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[13]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[14]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
|
||||||
|
connect_debug_port u_ila_0/probe4 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
|
||||||
|
connect_debug_port u_ila_0/probe5 [get_nets [list {mac_test0/mac_top0/mac_rx0/ip_total_data_length[0]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[1]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[2]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[3]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[4]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[5]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[6]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[7]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[8]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[9]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[10]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[11]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[12]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[13]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[14]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
|
||||||
|
connect_debug_port u_ila_0/probe6 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_datain[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
|
||||||
|
connect_debug_port u_ila_0/probe7 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_send_data_length[0]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[1]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[2]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[3]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[4]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[5]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[6]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[7]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[8]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[9]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[10]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[11]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[12]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[13]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[14]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
|
||||||
|
connect_debug_port u_ila_0/probe8 [get_nets [list {mac_test0/mac_top0/mac_tx0/ram_wr_data[0]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[1]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[2]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[3]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[4]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[5]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[6]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[7]}]]
|
||||||
|
connect_debug_port u_ila_0/probe9 [get_nets [list {mac_test0/mac_top0/mac_tx0/mac_tx_data[0]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[1]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[2]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[3]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[4]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[5]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[6]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[7]}]]
|
||||||
|
connect_debug_port u_ila_0/probe10 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
|
||||||
|
connect_debug_port u_ila_0/probe19 [get_nets [list mac_test0/mac_top0/mac_tx0/almost_full]]
|
||||||
|
connect_debug_port u_ila_0/probe27 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_data_valid]]
|
||||||
|
connect_debug_port u_ila_0/probe28 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_send_end]]
|
||||||
|
connect_debug_port u_ila_0/probe29 [get_nets [list mac_test0/mac_top0/mac_tx0/ram_wr_en]]
|
||||||
|
connect_debug_port u_ila_0/probe30 [get_nets [list mac_test0/mac_top0/mac_rx0/udp0/ram_wr_en]]
|
||||||
|
connect_debug_port u_ila_0/probe33 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_ram_data_req]]
|
||||||
|
connect_debug_port u_ila_0/probe34 [get_nets [list mac_test0/mac_top0/mac_rx0/udp_rec_data_valid]]
|
||||||
|
connect_debug_port u_ila_0/probe35 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_end]]
|
||||||
|
connect_debug_port u_ila_0/probe36 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_req]]
|
||||||
|
|
||||||
|
connect_debug_port u_ila_0/probe9 [get_nets [list {m_axis_rx_tdata_OBUF[0]} {m_axis_rx_tdata_OBUF[1]} {m_axis_rx_tdata_OBUF[2]} {m_axis_rx_tdata_OBUF[3]} {m_axis_rx_tdata_OBUF[4]} {m_axis_rx_tdata_OBUF[5]} {m_axis_rx_tdata_OBUF[6]} {m_axis_rx_tdata_OBUF[7]}]]
|
||||||
|
connect_debug_port u_ila_0/probe26 [get_nets [list m_axis_rx_tlast_OBUF]]
|
||||||
|
connect_debug_port u_ila_0/probe27 [get_nets [list m_axis_rx_tvalid_OBUF]]
|
||||||
|
|
||||||
|
|
||||||
|
create_debug_core u_ila_0 ila
|
||||||
|
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||||
|
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||||
|
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||||
|
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
||||||
|
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||||
|
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||||
|
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||||
|
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||||
|
connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
|
||||||
|
connect_debug_port u_ila_0/probe0 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe1]
|
||||||
|
connect_debug_port u_ila_0/probe1 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
|
||||||
|
connect_debug_port u_ila_0/probe2 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe3]
|
||||||
|
connect_debug_port u_ila_0/probe3 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe4]
|
||||||
|
connect_debug_port u_ila_0/probe4 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe5]
|
||||||
|
connect_debug_port u_ila_0/probe5 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||||
|
set_property port_width 16 [get_debug_ports u_ila_0/probe6]
|
||||||
|
connect_debug_port u_ila_0/probe6 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe7]
|
||||||
|
connect_debug_port u_ila_0/probe7 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||||
|
set_property port_width 2 [get_debug_ports u_ila_0/probe8]
|
||||||
|
connect_debug_port u_ila_0/probe8 [get_nets [list {axis_mac_inst/rx_state[0]} {axis_mac_inst/rx_state[1]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||||
|
set_property port_width 16 [get_debug_ports u_ila_0/probe9]
|
||||||
|
connect_debug_port u_ila_0/probe9 [get_nets [list {axis_mac_inst/rx_payload_len[0]} {axis_mac_inst/rx_payload_len[1]} {axis_mac_inst/rx_payload_len[2]} {axis_mac_inst/rx_payload_len[3]} {axis_mac_inst/rx_payload_len[4]} {axis_mac_inst/rx_payload_len[5]} {axis_mac_inst/rx_payload_len[6]} {axis_mac_inst/rx_payload_len[7]} {axis_mac_inst/rx_payload_len[8]} {axis_mac_inst/rx_payload_len[9]} {axis_mac_inst/rx_payload_len[10]} {axis_mac_inst/rx_payload_len[11]} {axis_mac_inst/rx_payload_len[12]} {axis_mac_inst/rx_payload_len[13]} {axis_mac_inst/rx_payload_len[14]} {axis_mac_inst/rx_payload_len[15]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||||
|
set_property port_width 16 [get_debug_ports u_ila_0/probe10]
|
||||||
|
connect_debug_port u_ila_0/probe10 [get_nets [list {axis_mac_inst/rx_index[0]} {axis_mac_inst/rx_index[1]} {axis_mac_inst/rx_index[2]} {axis_mac_inst/rx_index[3]} {axis_mac_inst/rx_index[4]} {axis_mac_inst/rx_index[5]} {axis_mac_inst/rx_index[6]} {axis_mac_inst/rx_index[7]} {axis_mac_inst/rx_index[8]} {axis_mac_inst/rx_index[9]} {axis_mac_inst/rx_index[10]} {axis_mac_inst/rx_index[11]} {axis_mac_inst/rx_index[12]} {axis_mac_inst/rx_index[13]} {axis_mac_inst/rx_index[14]} {axis_mac_inst/rx_index[15]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe11]
|
||||||
|
connect_debug_port u_ila_0/probe11 [get_nets [list {axis_mac_inst/m_axis_rx_tdata[0]} {axis_mac_inst/m_axis_rx_tdata[1]} {axis_mac_inst/m_axis_rx_tdata[2]} {axis_mac_inst/m_axis_rx_tdata[3]} {axis_mac_inst/m_axis_rx_tdata[4]} {axis_mac_inst/m_axis_rx_tdata[5]} {axis_mac_inst/m_axis_rx_tdata[6]} {axis_mac_inst/m_axis_rx_tdata[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe12]
|
||||||
|
connect_debug_port u_ila_0/probe12 [get_nets [list {axis_mac_inst/mac_top0/mac_tx0/mac_tx_data[0]} {axis_mac_inst/mac_top0/mac_tx0/mac_tx_data[1]} {axis_mac_inst/mac_top0/mac_tx0/mac_tx_data[2]} {axis_mac_inst/mac_top0/mac_tx0/mac_tx_data[3]} {axis_mac_inst/mac_top0/mac_tx0/mac_tx_data[4]} {axis_mac_inst/mac_top0/mac_tx0/mac_tx_data[5]} {axis_mac_inst/mac_top0/mac_tx0/mac_tx_data[6]} {axis_mac_inst/mac_top0/mac_tx0/mac_tx_data[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||||
|
set_property port_width 16 [get_debug_ports u_ila_0/probe13]
|
||||||
|
connect_debug_port u_ila_0/probe13 [get_nets [list {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[0]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[1]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[2]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[3]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[4]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[5]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[6]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[7]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[8]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[9]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[10]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[11]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[12]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[13]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[14]} {axis_mac_inst/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||||
|
set_property port_width 11 [get_debug_ports u_ila_0/probe14]
|
||||||
|
connect_debug_port u_ila_0/probe14 [get_nets [list {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe15]
|
||||||
|
connect_debug_port u_ila_0/probe15 [get_nets [list {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||||
|
set_property port_width 16 [get_debug_ports u_ila_0/probe16]
|
||||||
|
connect_debug_port u_ila_0/probe16 [get_nets [list {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[0]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[1]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[2]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[3]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[4]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[5]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[6]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[7]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[8]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[9]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[10]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[11]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[12]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[13]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[14]} {axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe17]
|
||||||
|
connect_debug_port u_ila_0/probe17 [get_nets [list {axis_mac_inst/mac_top0/mac_rx0/mac_rx_dataout[0]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_dataout[1]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_dataout[2]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_dataout[3]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_dataout[4]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_dataout[5]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_dataout[6]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||||
|
set_property port_width 16 [get_debug_ports u_ila_0/probe18]
|
||||||
|
connect_debug_port u_ila_0/probe18 [get_nets [list {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[0]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[1]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[2]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[3]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[4]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[5]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[6]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[7]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[8]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[9]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[10]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[11]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[12]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[13]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[14]} {axis_mac_inst/mac_top0/mac_rx0/ip_total_data_length[15]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||||
|
set_property port_width 8 [get_debug_ports u_ila_0/probe19]
|
||||||
|
connect_debug_port u_ila_0/probe19 [get_nets [list {axis_mac_inst/mac_top0/mac_rx0/mac_rx_datain[0]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_datain[1]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_datain[2]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_datain[3]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_datain[4]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_datain[5]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_datain[6]} {axis_mac_inst/mac_top0/mac_rx0/mac_rx_datain[7]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||||
|
set_property port_width 11 [get_debug_ports u_ila_0/probe20]
|
||||||
|
connect_debug_port u_ila_0/probe20 [get_nets [list {axis_mac_inst/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {axis_mac_inst/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {axis_mac_inst/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {axis_mac_inst/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {axis_mac_inst/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {axis_mac_inst/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {axis_mac_inst/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {axis_mac_inst/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {axis_mac_inst/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {axis_mac_inst/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {axis_mac_inst/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
|
||||||
|
connect_debug_port u_ila_0/probe21 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/almost_full]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
|
||||||
|
connect_debug_port u_ila_0/probe22 [get_nets [list arbi_inst/rx_buffer_inst/e10_100_rx_dv]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
|
||||||
|
connect_debug_port u_ila_0/probe23 [get_nets [list arbi_inst/e_rx_dv]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
|
||||||
|
connect_debug_port u_ila_0/probe24 [get_nets [list arbi_inst/e_tx_en]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
|
||||||
|
connect_debug_port u_ila_0/probe25 [get_nets [list arbi_inst/gmii_rx_dv]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
|
||||||
|
connect_debug_port u_ila_0/probe26 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d0]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
|
||||||
|
connect_debug_port u_ila_0/probe27 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d1]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
|
||||||
|
connect_debug_port u_ila_0/probe28 [get_nets [list arbi_inst/gmii_tx_en]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
||||||
|
connect_debug_port u_ila_0/probe29 [get_nets [list axis_mac_inst/m_axis_rx_tlast]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
||||||
|
connect_debug_port u_ila_0/probe30 [get_nets [list axis_mac_inst/m_axis_rx_tvalid]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
||||||
|
connect_debug_port u_ila_0/probe31 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/mac_data_valid]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
||||||
|
connect_debug_port u_ila_0/probe32 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/mac_send_end]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
||||||
|
connect_debug_port u_ila_0/probe33 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_0]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
||||||
|
connect_debug_port u_ila_0/probe34 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_1]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
||||||
|
connect_debug_port u_ila_0/probe35 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_2]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
||||||
|
connect_debug_port u_ila_0/probe36 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_3]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
||||||
|
connect_debug_port u_ila_0/probe37 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_4]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
||||||
|
connect_debug_port u_ila_0/probe38 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_5]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
||||||
|
connect_debug_port u_ila_0/probe39 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_6]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
||||||
|
connect_debug_port u_ila_0/probe40 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_7]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
||||||
|
connect_debug_port u_ila_0/probe41 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_8]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
||||||
|
connect_debug_port u_ila_0/probe42 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_9]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
||||||
|
connect_debug_port u_ila_0/probe43 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_10]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
||||||
|
connect_debug_port u_ila_0/probe44 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_11]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
||||||
|
connect_debug_port u_ila_0/probe45 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_12]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
||||||
|
connect_debug_port u_ila_0/probe46 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_13]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
||||||
|
connect_debug_port u_ila_0/probe47 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_14]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
||||||
|
connect_debug_port u_ila_0/probe48 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_15]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
||||||
|
connect_debug_port u_ila_0/probe49 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_16]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
||||||
|
connect_debug_port u_ila_0/probe50 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_17]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
||||||
|
connect_debug_port u_ila_0/probe51 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_18]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
||||||
|
connect_debug_port u_ila_0/probe52 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_19]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
||||||
|
connect_debug_port u_ila_0/probe53 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_20]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
||||||
|
connect_debug_port u_ila_0/probe54 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_21]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
||||||
|
connect_debug_port u_ila_0/probe55 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_22]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
||||||
|
connect_debug_port u_ila_0/probe56 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_23]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
||||||
|
connect_debug_port u_ila_0/probe57 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_24]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
||||||
|
connect_debug_port u_ila_0/probe58 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/n_0_25]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
||||||
|
connect_debug_port u_ila_0/probe59 [get_nets [list axis_mac_inst/mac_top0/mac_rx0/udp0/ram_wr_en]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
||||||
|
connect_debug_port u_ila_0/probe60 [get_nets [list arbi_inst/tx_buffer_inst/tx_rden]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
||||||
|
connect_debug_port u_ila_0/probe61 [get_nets [list arbi_inst/tx_buffer_inst/tx_wren]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
||||||
|
connect_debug_port u_ila_0/probe62 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/udp_ram_data_req]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
||||||
|
connect_debug_port u_ila_0/probe63 [get_nets [list axis_mac_inst/mac_top0/mac_rx0/udp_rec_data_valid]]
|
||||||
|
create_debug_port u_ila_0 probe
|
||||||
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
||||||
|
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
||||||
|
connect_debug_port u_ila_0/probe64 [get_nets [list axis_mac_inst/mac_top0/mac_tx0/udp_tx_end]]
|
||||||
|
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||||
|
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||||
|
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||||
|
connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]
|
||||||
@ -1,229 +0,0 @@
|
|||||||
`timescale 1 ns / 1 ns
|
|
||||||
|
|
||||||
module axis_mac
|
|
||||||
(
|
|
||||||
input rst_n,
|
|
||||||
input gmii_tx_clk,
|
|
||||||
input gmii_rx_clk,
|
|
||||||
input gmii_rx_dv,
|
|
||||||
input [7:0] gmii_rxd,
|
|
||||||
|
|
||||||
output reg gmii_tx_en,
|
|
||||||
output reg [7:0] gmii_txd,
|
|
||||||
|
|
||||||
// AXI-stream RX output (clock domain = gmii_rx_clk)
|
|
||||||
(* MARK_DEBUG="true" *)output reg [7:0] m_axis_rx_tdata,
|
|
||||||
(* MARK_DEBUG="true" *)output reg m_axis_rx_tvalid,
|
|
||||||
input wire m_axis_rx_tready,
|
|
||||||
(* MARK_DEBUG="true" *)output reg m_axis_rx_tlast
|
|
||||||
);
|
|
||||||
|
|
||||||
// ----------------------------------------------------------------
|
|
||||||
// GMII RX input registering
|
|
||||||
// ----------------------------------------------------------------
|
|
||||||
reg gmii_rx_dv_d0;
|
|
||||||
reg [7:0] gmii_rxd_d0;
|
|
||||||
|
|
||||||
always @(posedge gmii_rx_clk or negedge rst_n) begin
|
|
||||||
if (!rst_n) begin
|
|
||||||
gmii_rx_dv_d0 <= 1'b0;
|
|
||||||
gmii_rxd_d0 <= 8'd0;
|
|
||||||
end else begin
|
|
||||||
gmii_rx_dv_d0 <= gmii_rx_dv;
|
|
||||||
gmii_rxd_d0 <= gmii_rxd;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// ----------------------------------------------------------------
|
|
||||||
// TX path from mac_top
|
|
||||||
// ----------------------------------------------------------------
|
|
||||||
wire gmii_tx_en_tmp;
|
|
||||||
wire [7:0] gmii_txd_tmp;
|
|
||||||
|
|
||||||
always @(posedge gmii_tx_clk or negedge rst_n) begin
|
|
||||||
if (!rst_n) begin
|
|
||||||
gmii_tx_en <= 1'b0;
|
|
||||||
gmii_txd <= 8'd0;
|
|
||||||
end else begin
|
|
||||||
gmii_tx_en <= gmii_tx_en_tmp;
|
|
||||||
gmii_txd <= gmii_txd_tmp;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// ----------------------------------------------------------------
|
|
||||||
// Unused user TX path into mac_top
|
|
||||||
// We disable user UDP TX for now.
|
|
||||||
// ARP replies and ICMP replies inside mac_top still work.
|
|
||||||
// ----------------------------------------------------------------
|
|
||||||
wire udp_ram_data_req;
|
|
||||||
wire udp_tx_end;
|
|
||||||
wire almost_full;
|
|
||||||
wire mac_send_end;
|
|
||||||
wire arp_found;
|
|
||||||
wire mac_not_exist;
|
|
||||||
|
|
||||||
wire [7:0] udp_rec_ram_rdata;
|
|
||||||
reg [10:0] udp_rec_ram_read_addr;
|
|
||||||
wire [15:0] udp_rec_data_length;
|
|
||||||
wire udp_rec_data_valid;
|
|
||||||
|
|
||||||
wire [7:0] tx_ram_wr_data = 8'd0;
|
|
||||||
wire tx_ram_wr_en = 1'b0;
|
|
||||||
wire [15:0] udp_send_data_length = 16'd0;
|
|
||||||
wire udp_tx_req = 1'b0;
|
|
||||||
wire arp_request_req = 1'b0;
|
|
||||||
|
|
||||||
mac_top mac_top0 (
|
|
||||||
.gmii_tx_clk (gmii_tx_clk),
|
|
||||||
.gmii_rx_clk (gmii_rx_clk),
|
|
||||||
.rst_n (rst_n),
|
|
||||||
|
|
||||||
.source_mac_addr (48'h00_0a_35_01_fe_c0),
|
|
||||||
.TTL (8'h80),
|
|
||||||
.source_ip_addr (32'hc0a80002), // 192.168.0.2
|
|
||||||
.destination_ip_addr (32'hc0a80003), // 192.168.0.3 (не используется для user TX пока)
|
|
||||||
.udp_send_source_port (16'h1f90), // 8080
|
|
||||||
.udp_send_destination_port (16'h1f90), // 8080
|
|
||||||
|
|
||||||
.ram_wr_data (tx_ram_wr_data),
|
|
||||||
.ram_wr_en (tx_ram_wr_en),
|
|
||||||
.udp_ram_data_req (udp_ram_data_req),
|
|
||||||
.udp_send_data_length (udp_send_data_length),
|
|
||||||
.udp_tx_end (udp_tx_end),
|
|
||||||
.almost_full (almost_full),
|
|
||||||
|
|
||||||
.udp_tx_req (udp_tx_req),
|
|
||||||
.arp_request_req (arp_request_req),
|
|
||||||
|
|
||||||
.mac_send_end (mac_send_end),
|
|
||||||
.mac_data_valid (gmii_tx_en_tmp),
|
|
||||||
.mac_tx_data (gmii_txd_tmp),
|
|
||||||
|
|
||||||
.rx_dv (gmii_rx_dv_d0),
|
|
||||||
.mac_rx_datain (gmii_rxd_d0),
|
|
||||||
|
|
||||||
.udp_rec_ram_rdata (udp_rec_ram_rdata),
|
|
||||||
.udp_rec_ram_read_addr (udp_rec_ram_read_addr),
|
|
||||||
.udp_rec_data_length (udp_rec_data_length),
|
|
||||||
.udp_rec_data_valid (udp_rec_data_valid),
|
|
||||||
|
|
||||||
.arp_found (arp_found),
|
|
||||||
.mac_not_exist (mac_not_exist)
|
|
||||||
);
|
|
||||||
|
|
||||||
// ----------------------------------------------------------------
|
|
||||||
// Detect "new packet ready" on udp_rec_data_valid rising edge
|
|
||||||
// ----------------------------------------------------------------
|
|
||||||
reg udp_rec_data_valid_d0;
|
|
||||||
|
|
||||||
always @(posedge gmii_rx_clk or negedge rst_n) begin
|
|
||||||
if (!rst_n)
|
|
||||||
udp_rec_data_valid_d0 <= 1'b0;
|
|
||||||
else
|
|
||||||
udp_rec_data_valid_d0 <= udp_rec_data_valid;
|
|
||||||
end
|
|
||||||
|
|
||||||
wire udp_pkt_done = udp_rec_data_valid & ~udp_rec_data_valid_d0;
|
|
||||||
|
|
||||||
// ----------------------------------------------------------------
|
|
||||||
// RX RAM -> AXI-stream bridge
|
|
||||||
//
|
|
||||||
// Assumption:
|
|
||||||
// udp_rec_data_length includes 8-byte UDP header,
|
|
||||||
// so payload length = udp_rec_data_length - 8
|
|
||||||
//
|
|
||||||
// This implementation is simple and safe:
|
|
||||||
// - start on udp_pkt_done
|
|
||||||
// - read bytes 0 .. payload_len-1 from RX RAM
|
|
||||||
// - output them on AXIS
|
|
||||||
//
|
|
||||||
// Because the BRAM read port is synchronous, this bridge may insert
|
|
||||||
// bubbles between bytes. For first bring-up this is fine.
|
|
||||||
// ----------------------------------------------------------------
|
|
||||||
localparam RX_IDLE = 2'd0;
|
|
||||||
localparam RX_ADDR = 2'd1;
|
|
||||||
localparam RX_DATA = 2'd2;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) reg [1:0] rx_state;
|
|
||||||
(* MARK_DEBUG="true" *) reg [15:0] rx_payload_len;
|
|
||||||
(* MARK_DEBUG="true" *) reg [15:0] rx_index;
|
|
||||||
|
|
||||||
always @(posedge gmii_rx_clk or negedge rst_n) begin
|
|
||||||
if (!rst_n) begin
|
|
||||||
rx_state <= RX_IDLE;
|
|
||||||
rx_payload_len <= 16'd0;
|
|
||||||
rx_index <= 16'd0;
|
|
||||||
udp_rec_ram_read_addr <= 11'd0;
|
|
||||||
|
|
||||||
m_axis_rx_tdata <= 8'd0;
|
|
||||||
m_axis_rx_tvalid <= 1'b0;
|
|
||||||
m_axis_rx_tlast <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
case (rx_state)
|
|
||||||
RX_IDLE: begin
|
|
||||||
m_axis_rx_tvalid <= 1'b0;
|
|
||||||
m_axis_rx_tlast <= 1'b0;
|
|
||||||
rx_index <= 16'd0;
|
|
||||||
udp_rec_ram_read_addr <= 11'd0;
|
|
||||||
|
|
||||||
if (udp_pkt_done) begin
|
|
||||||
// protect against pathological short values
|
|
||||||
if (udp_rec_data_length > 16'd8) begin
|
|
||||||
rx_payload_len <= udp_rec_data_length - 16'd8;
|
|
||||||
udp_rec_ram_read_addr <= 11'd0; // issue read for byte 0
|
|
||||||
rx_state <= RX_ADDR;
|
|
||||||
end else begin
|
|
||||||
rx_payload_len <= 16'd0;
|
|
||||||
rx_state <= RX_IDLE;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// one cycle for synchronous BRAM read latency
|
|
||||||
RX_ADDR: begin
|
|
||||||
m_axis_rx_tvalid <= 1'b0;
|
|
||||||
m_axis_rx_tlast <= 1'b0;
|
|
||||||
rx_state <= RX_DATA;
|
|
||||||
end
|
|
||||||
|
|
||||||
RX_DATA: begin
|
|
||||||
// hold valid until accepted
|
|
||||||
if (m_axis_rx_tvalid && !m_axis_rx_tready) begin
|
|
||||||
m_axis_rx_tvalid <= m_axis_rx_tvalid;
|
|
||||||
m_axis_rx_tlast <= m_axis_rx_tlast;
|
|
||||||
end else begin
|
|
||||||
// present current byte from RAM
|
|
||||||
m_axis_rx_tdata <= udp_rec_ram_rdata;
|
|
||||||
m_axis_rx_tvalid <= 1'b1;
|
|
||||||
m_axis_rx_tlast <= (rx_index == rx_payload_len - 1);
|
|
||||||
|
|
||||||
if (rx_index == rx_payload_len - 1) begin
|
|
||||||
// last byte accepted immediately if ready=1,
|
|
||||||
// otherwise valid/last remain asserted until ready
|
|
||||||
if (m_axis_rx_tready) begin
|
|
||||||
m_axis_rx_tvalid <= 1'b0;
|
|
||||||
m_axis_rx_tlast <= 1'b0;
|
|
||||||
rx_state <= RX_IDLE;
|
|
||||||
end
|
|
||||||
end else begin
|
|
||||||
if (m_axis_rx_tready) begin
|
|
||||||
rx_index <= rx_index + 1'b1;
|
|
||||||
udp_rec_ram_read_addr <= rx_index + 1'b1; // next byte
|
|
||||||
rx_state <= RX_ADDR;
|
|
||||||
m_axis_rx_tvalid <= 1'b0;
|
|
||||||
m_axis_rx_tlast <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
default: begin
|
|
||||||
rx_state <= RX_IDLE;
|
|
||||||
m_axis_rx_tvalid <= 1'b0;
|
|
||||||
m_axis_rx_tlast <= 1'b0;
|
|
||||||
end
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
Reference in New Issue
Block a user