rtl: generator added

rtl/generator/src/generator.sv

@@ -0,0 +1,99 @@
+`timescale 1ns / 1ps
+
+
+module generator
+#(
+    parameter DATA_WIDTH = 14
+    )
+(
+    input clk_in,
+    input rst,
+    input start,
+    input [31:0]           pulse_width,
+    input [31:0]           pulse_period,
+    input [DATA_WIDTH-1:0] pulse_height,
+    input [15:0]           pulse_num,
+    
+    output pulse,
+    output[DATA_WIDTH-1:0] pulse_height_out
+    
+    );
+    
+    logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
+    logic pulse_reg;
+    
+    logic [31:0] pulse_width_reg, pulse_period_reg;
+    logic [15:0] pulse_num_reg;
+    
+    logic enable;
+    logic [15:0] cnt_pulse_num;
+    logic [31:0] cnt_period;
+    
+    logic start_d;
+
+    always @(posedge clk_in) begin
+        start_d <= start;
+    end
+
+    wire start_pulse = start & ~start_d;
+
+    
+    always @(posedge clk_in) begin
+        if (rst) begin
+            pulse_reg <= '0;
+            pulse_height_reg <= 0;
+            pulse_height_out_reg <= '0;
+            
+            pulse_width_reg <= '0;
+            pulse_period_reg <= '0;
+            pulse_num_reg <= '0;
+            enable <= 0;
+            cnt_pulse_num <= '0;
+            cnt_period <= '0;
+        end else begin
+            if (start) begin
+                enable <= 1'b1;
+//                pulse_width_reg <= pulse_width;
+//                pulse_period_reg <= pulse_period;
+//                pulse_num_reg <= pulse_num;
+//                pulse_height_reg <= pulse_height;
+                
+                cnt_pulse_num <= '0;
+                cnt_period <= '0;
+            end
+            if (enable) begin
+                pulse_reg <= 1;
+                
+                pulse_width_reg <= pulse_width;
+                pulse_period_reg <= pulse_period;
+                pulse_num_reg <= pulse_num;
+                pulse_height_reg <= pulse_height;
+                
+                if (pulse_reg) begin
+                
+                if (cnt_period < pulse_width_reg) begin
+                    pulse_height_out_reg <= pulse_height_reg;
+                end else begin
+                    pulse_height_out_reg <= '0;
+                end
+                if (cnt_period == pulse_period_reg - 1) begin
+                    cnt_period <= 0;
+                    if (cnt_pulse_num == pulse_num_reg - 1) begin
+                        enable <= 0;
+                        pulse_reg <= 0;
+                    end else begin
+                        cnt_pulse_num <= cnt_pulse_num + 1;
+                    end
+                end else begin
+                    cnt_period <= cnt_period + 1;
+                end
+                
+                end
+            end
+        end
+    end
+    
+    assign pulse_height_out = pulse_height_out_reg;
+    assign pulse = pulse_reg;
+    
+endmodule

rtl/generator/tests/generator_tb.sv

@@ -0,0 +1,105 @@
+`timescale 1ns / 1ps
+
+module generator_tb;
+
+    parameter DATA_WIDTH = 14;
+    parameter CLK_PERIOD = 16;
+
+    logic clk;
+    logic rst;
+    logic start;
+
+    logic [31:0] pulse_width;
+    logic [31:0] pulse_period;
+    logic [DATA_WIDTH-1:0] pulse_height;
+    logic [15:0] pulse_num;
+
+    logic pulse;
+    logic [DATA_WIDTH-1:0] pulse_height_out;
+
+    // DUT
+    generator #(
+        .DATA_WIDTH(DATA_WIDTH)
+    ) dut (
+        .clk_in(clk),
+        .rst(rst),
+        .start(start),
+        .pulse_width(pulse_width),
+        .pulse_period(pulse_period),
+        .pulse_height(pulse_height),
+        .pulse_num(pulse_num),
+        .pulse(pulse),
+        .pulse_height_out(pulse_height_out)
+    );
+
+    // Clock
+    initial begin
+        clk = 0;
+        forever #(CLK_PERIOD/2) clk = ~clk;
+    end
+
+    initial begin
+        $display("\n=== GENERATOR TEST ===\n");
+
+        rst = 1;
+        start = 0;
+
+        pulse_width  = 0;
+        pulse_period = 0;
+        pulse_height = 0;
+        pulse_num    = 0;
+
+        repeat(5) @(posedge clk);
+        rst = 0;
+
+        // --- Test 1 ---
+        // 3 clk 1, 5 clk 0,  4 pulses
+       repeat(2) @(posedge clk);
+        pulse_width  = 3;
+        pulse_period = 8;
+        pulse_num    = 4;
+        pulse_height = 14'h3FF;
+        start = 1;
+
+       repeat(1) @(posedge clk);
+        start = 0;
+
+        repeat(50) @(posedge clk);
+
+        // --- Test 2 ---
+        $display("\n--- SECOND RUN ---\n");
+
+        @(posedge clk);
+        pulse_width  = 2;
+        pulse_period = 5;
+        pulse_num    = 3;
+        pulse_height = 14'h155;
+        start = 1;
+
+        @(posedge clk);
+        start = 0;
+
+        repeat(40) @(posedge clk);
+        
+         pulse_width  = 3;
+        pulse_period = 8;
+        pulse_num    = 4;
+        pulse_height = 14'h3FF;
+        start = 1;
+
+       repeat(1) @(posedge clk);
+        start = 0;
+
+        repeat(50) @(posedge clk);
+
+        $display("\n=== TEST FINISHED ===");
+        $finish;
+    end
+
+    // Display
+    always @(posedge clk) begin
+        $display("t=%0t | pulse=%0b | height=%h",
+                  $time, pulse, pulse_height_out);
+    end
+
+endmodule