From fd4b17be0d27e453668e210b7e8005a6ebecb0e1 Mon Sep 17 00:00:00 2001
From: otroubi <ilianovadasha@gmail.com>
Date: Mon, 27 Jul 2026 19:25:09 +0300
Subject: [PATCH] debugging shaper

---
 rtl/controller/src/shaper_axis_status.sv | 26 ++++++++++++++----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/rtl/controller/src/shaper_axis_status.sv b/rtl/controller/src/shaper_axis_status.sv
index cfb585e..5bad170 100644
--- a/rtl/controller/src/shaper_axis_status.sv
+++ b/rtl/controller/src/shaper_axis_status.sv
@@ -16,11 +16,13 @@ module shaper_axis_status #(
 
 typedef enum logic [0:0] {
     IDLE,
-    WAIT_VALID
+    WAIT_TAKE
 } wr_state;
 
 wr_state state;
 
+logic [31:0] data_reg;
+
 always @(posedge clk) begin
     if (!rst_n) begin
         state      <= IDLE;
@@ -28,22 +30,24 @@ always @(posedge clk) begin
         busy       <= 1'b0;
         handshake  <= 1'b0;
         data_out   <= '0;
+        data_reg   <= '0;
     end else begin
         case (state) 
         IDLE: begin
-                handshake <= 1'b0;
-                if (take) begin
-                    ready <= 1'b1;
-                    busy <= 1'b1;
-                     state <= WAIT_VALID;
+                ready <= 1'b1;
+                if (valid) begin
+                    busy <= 1'b0;
+                    data_reg <= data_in;
+                    handshake <= 1'b1;
+                     state <= WAIT_TAKE;
                 end
               end
-        WAIT_VALID: begin
-                        if (valid) begin
-                            data_out <= data_in;
+        WAIT_TAKE: begin
+                        if (take) begin
+                            data_out <= data_reg;
                             ready <= 1'b0;
-                            handshake <= 1'b1;
-                            busy <= 1'b0;
+                            handshake <= 1'b0;
+                            busy <= 1'b1;
                             state <= IDLE;
                         end
                     end