controller's changes

rtl/controller/src/controller.sv

@@ -79,7 +79,7 @@ module control #(
         end
     end
 
-    assign ctrl_rst     = eth_rst_ff2;
+    assign ctrl_rst     = rst_ff2;
     assign dac_rst_int = dac_rst_ff2;
     assign adc_rst_int = adc_rst_ff2;
 
@@ -92,7 +92,7 @@ module control #(
     logic cfg_req_toggle_dac;
     logic cfg_req_toggle_adc;
 
-    // ACK toggles DAC/ADC -> contrl
+    // ACK toggles DAC/ADC -> cntrl
     logic cfg_ack_toggle_dac;
     logic cfg_ack_toggle_adc;
 
@@ -122,7 +122,7 @@ module control #(
         end
     end
 
-    // finish event: ADC -> ETH via toggle CDC
+    // finish event: ADC -> cntrl via toggle CDC
     logic finish_toggle_adc;
     logic finish_meta, finish_sync, finish_sync_d;
 
@@ -143,8 +143,8 @@ module control #(
             finish_sync_d <= 1'b0;
         end else begin
             finish_meta   <= finish_toggle_adc;
-            finish_sync   <= finish_meta_eth;
-            finish_sync_d <= finish_sync_eth;
+            finish_sync   <= finish_meta;
+            finish_sync_d <= finish_sync;
         end
     end
 
@@ -183,7 +183,7 @@ module control #(
         end
     end
 
-    // ETH -> ADC: start/reset event sync
+    // cntrl -> ADC: start/reset event sync
     (* ASYNC_REG = "TRUE" *) logic start_meta_adc, start_sync_adc;
     logic start_sync_adc_d;
     (* ASYNC_REG = "TRUE" *) logic rst_meta_adc,   rst_sync_adc;

rtl/controller/src/controller_wrapper_axil.sv

@@ -32,7 +32,7 @@ module controller_wrapper_axil #(
     output logic                       adc_rst
 );
 
-    logic start, rst_soft;
+    logic start, rst_soft, send;
     logic [31:0] pulse_width, pulse_period, pulse_num, pulse_height_raw, pulse_period_ADC;
     logic [7:0] busy, error_code;
     logic [31:0] desc_read_addr, desc_read_len, desc_read_config, status_read;
@@ -48,6 +48,7 @@ module controller_wrapper_axil #(
         .s_axil(s_axil),
 
         .start_o(start),
+        .send_o(send),
         .pulse_width_o(pulse_width),
         .pulse_period_o(pulse_period),
         .pulse_num_o(pulse_num),
@@ -89,12 +90,12 @@ module controller_wrapper_axil #(
         .DAC_DATA_WIDTH(DAC_DATA_WIDTH)
     )
     controller (
-        .ctrl_clk(),
-        .dac_clk_in(),
-        .adc_clk_in(),
-        .rst_n(),
-        .rst_soft(),
-        .finish(),
+        .ctrl_clk(ctrl_clk),
+        .dac_clk_in(dac_clk_in),
+        .adc_clk_in(adc_clk_in),
+        .rst_n(rst_n),
+        .rst_soft(rst_soft),
+        .finish(finish),
         .cfg_bus(cfg_bus),
         .start(start),
 

rtl/controller/src/dma_controller.sv

@@ -46,4 +46,27 @@ input [127:0] status_write,
     input wire [3:0]                 m_axis_write_desc_status_error,
     input wire                       m_axis_write_desc_status_valid
 );
+
+typedef enum logic [0:0] {
+    IDLE,
+    WAIT_READY
+} wr_state;
+
+wr_state state;
+
+always @(posedge clk) begin
+    if (rst) begin
+
+    end else begin
+        case (state)
+            IDLE: begin
+                    if (send) begin
+
+                    end
+            WAIT_READY: begin
+
+                        end
+        endcase
+    end
+
 endmodule