controller's changes

rtl/controller/src/controller.sv

@@ -79,7 +79,7 @@ module control #(
         end
     end
 
-    assign ctrl_rst     = eth_rst_ff2;
+    assign ctrl_rst     = rst_ff2;
     assign dac_rst_int = dac_rst_ff2;
     assign adc_rst_int = adc_rst_ff2;
 
@@ -92,7 +92,7 @@ module control #(
     logic cfg_req_toggle_dac;
     logic cfg_req_toggle_adc;
 
-    // ACK toggles DAC/ADC -> contrl
+    // ACK toggles DAC/ADC -> cntrl
     logic cfg_ack_toggle_dac;
     logic cfg_ack_toggle_adc;
 
@@ -122,7 +122,7 @@ module control #(
         end
     end
 
-    // finish event: ADC -> ETH via toggle CDC
+    // finish event: ADC -> cntrl via toggle CDC
     logic finish_toggle_adc;
     logic finish_meta, finish_sync, finish_sync_d;
 
@@ -143,8 +143,8 @@ module control #(
             finish_sync_d <= 1'b0;
         end else begin
             finish_meta   <= finish_toggle_adc;
-            finish_sync   <= finish_meta_eth;
-            finish_sync_d <= finish_sync_eth;
+            finish_sync   <= finish_meta;
+            finish_sync_d <= finish_sync;
         end
     end
 
@@ -183,7 +183,7 @@ module control #(
         end
     end
 
-    // ETH -> ADC: start/reset event sync
+    // cntrl -> ADC: start/reset event sync
     (* ASYNC_REG = "TRUE" *) logic start_meta_adc, start_sync_adc;
     logic start_sync_adc_d;
     (* ASYNC_REG = "TRUE" *) logic rst_meta_adc,   rst_sync_adc;