From f9f4a10cdfae6d53b73f49a70769c92482848798 Mon Sep 17 00:00:00 2001 From: Phil Date: Tue, 12 May 2026 13:23:42 +0300 Subject: [PATCH] infra: fix constraints - adc --- constraints/ax7102.xdc | 35 ++++++++++++++++++----------------- constraints/ax7a035b.xdc | 26 ++++++++++++++------------ 2 files changed, 32 insertions(+), 29 deletions(-) diff --git a/constraints/ax7102.xdc b/constraints/ax7102.xdc index d97d399..d8bec73 100644 --- a/constraints/ax7102.xdc +++ b/constraints/ax7102.xdc @@ -86,18 +86,18 @@ set_false_path -reset_path -from [get_clocks sys_clk_p] -to [get_clocks rx_clk] # === ADC an9238 (J4 header) === set_property PACKAGE_PIN K14 [get_ports ch2_clk] -set_property PACKAGE_PIN K13 [get_ports ch2_data[0]] -set_property PACKAGE_PIN H14 [get_ports ch2_data[1]] -set_property PACKAGE_PIN J14 [get_ports ch2_data[2]] -set_property PACKAGE_PIN H15 [get_ports ch2_data[3]] -set_property PACKAGE_PIN J15 [get_ports ch2_data[4]] -set_property PACKAGE_PIN G13 [get_ports ch2_data[5]] -set_property PACKAGE_PIN H13 [get_ports ch2_data[6]] -set_property PACKAGE_PIN J21 [get_ports ch2_data[7]] -set_property PACKAGE_PIN J20 [get_ports ch2_data[8]] -set_property PACKAGE_PIN G16 [get_ports ch2_data[9]] -set_property PACKAGE_PIN G15 [get_ports ch2_data[10]] -set_property PACKAGE_PIN H19 [get_ports ch2_data[11]] +set_property PACKAGE_PIN K13 [get_ports {ch2_data[0]}] +set_property PACKAGE_PIN H14 [get_ports {ch2_data[1]}] +set_property PACKAGE_PIN J14 [get_ports {ch2_data[2]}] +set_property PACKAGE_PIN H15 [get_ports {ch2_data[3]}] +set_property PACKAGE_PIN J15 [get_ports {ch2_data[4]}] +set_property PACKAGE_PIN G13 [get_ports {ch2_data[5]}] +set_property PACKAGE_PIN H13 [get_ports {ch2_data[6]}] +set_property PACKAGE_PIN J21 [get_ports {ch2_data[7]}] +set_property PACKAGE_PIN J20 [get_ports {ch2_data[8]}] +set_property PACKAGE_PIN G16 [get_ports {ch2_data[9]}] +set_property PACKAGE_PIN G15 [get_ports {ch2_data[10]}] +set_property PACKAGE_PIN H19 [get_ports {ch2_data[11]}] set_property PACKAGE_PIN J19 [get_ports ch2_otr] set_property PACKAGE_PIN J16 [get_ports ch1_data[1]] @@ -122,7 +122,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {ch1_data[*]}] set_property IOSTANDARD LVCMOS33 [get_ports ch1_clk] set_property IOSTANDARD LVCMOS33 [get_ports ch1_otr] -set_property SLEW FAST [get_ports {ch2_clk ch1_clk}] +set_property SLEW FAST [get_ports ch2_clk] @@ -148,8 +148,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {da1_data[*]}] set_property IOSTANDARD LVCMOS33 [get_ports {da1_wrt}] set_property IOSTANDARD LVCMOS33 [get_ports {da1_clk}] -set_property PACKAGE_PIN E14 [get_ports {da2_clk}] -set_property PACKAGE_PIN E13 [get_ports {da2_wrt}] +set_property PACKAGE_PIN E14 [get_ports da2_clk] +set_property PACKAGE_PIN E13 [get_ports da2_wrt] set_property PACKAGE_PIN D15 [get_ports {da2_data[13]}] set_property PACKAGE_PIN D14 [get_ports {da2_data[12]}] set_property PACKAGE_PIN B13 [get_ports {da2_data[11]}] @@ -165,7 +165,8 @@ set_property PACKAGE_PIN F19 [get_ports {da2_data[2]}] set_property PACKAGE_PIN A20 [get_ports {da2_data[1]}] set_property PACKAGE_PIN B20 [get_ports {da2_data[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {da2_clk}] -set_property IOSTANDARD LVCMOS33 [get_ports {da2_wrt}] +set_property IOSTANDARD LVCMOS33 [get_ports da2_clk] +set_property IOSTANDARD LVCMOS33 [get_ports da2_wrt] set_property IOSTANDARD LVCMOS33 [get_ports {da2_data[*]}] + diff --git a/constraints/ax7a035b.xdc b/constraints/ax7a035b.xdc index 2a0d1b3..4f01ef1 100644 --- a/constraints/ax7a035b.xdc +++ b/constraints/ax7a035b.xdc @@ -97,18 +97,18 @@ create_clock -period 8.000 [get_ports rgmii_rxc] # === ADC an9238 (J11 header) === set_property PACKAGE_PIN G21 [get_ports ch2_clk] -set_property PACKAGE_PIN G22 [get_ports ch2_data[0]] -set_property PACKAGE_PIN C22 [get_ports ch2_data[1]] -set_property PACKAGE_PIN B22 [get_ports ch2_data[2]] -set_property PACKAGE_PIN F19 [get_ports ch2_data[3]] -set_property PACKAGE_PIN F20 [get_ports ch2_data[4]] -set_property PACKAGE_PIN D20 [get_ports ch2_data[5]] -set_property PACKAGE_PIN C20 [get_ports ch2_data[6]] -set_property PACKAGE_PIN A18 [get_ports ch2_data[7]] -set_property PACKAGE_PIN A19 [get_ports ch2_data[8]] -set_property PACKAGE_PIN B20 [get_ports ch2_data[9]] -set_property PACKAGE_PIN A20 [get_ports ch2_data[10]] -set_property PACKAGE_PIN F18 [get_ports ch2_data[11]] +set_property PACKAGE_PIN G22 [get_ports {ch2_data[0]}] +set_property PACKAGE_PIN C22 [get_ports {ch2_data[1]}] +set_property PACKAGE_PIN B22 [get_ports {ch2_data[2]}] +set_property PACKAGE_PIN F19 [get_ports {ch2_data[3]}] +set_property PACKAGE_PIN F20 [get_ports {ch2_data[4]}] +set_property PACKAGE_PIN D20 [get_ports {ch2_data[5]}] +set_property PACKAGE_PIN C20 [get_ports {ch2_data[6]}] +set_property PACKAGE_PIN A18 [get_ports {ch2_data[7]}] +set_property PACKAGE_PIN A19 [get_ports {ch2_data[8]}] +set_property PACKAGE_PIN B20 [get_ports {ch2_data[9]}] +set_property PACKAGE_PIN A20 [get_ports {ch2_data[10]}] +set_property PACKAGE_PIN F18 [get_ports {ch2_data[11]}] set_property PACKAGE_PIN E18 [get_ports ch2_otr] set_property PACKAGE_PIN C18 [get_ports ch1_data[1]] set_property PACKAGE_PIN C19 [get_ports ch1_data[0]] @@ -136,3 +136,5 @@ set_property IOSTANDARD LVCMOS33 [get_ports ch1_otr] set_property PACKAGE_PIN E17 [get_ports debug_dac] set_property IOSTANDARD LVCMOS33 [get_ports debug_dac] + +