From f719533eb9df122b59b440e2346503948a037d68 Mon Sep 17 00:00:00 2001 From: otroubi Date: Thu, 30 Apr 2026 13:14:26 +0300 Subject: [PATCH] chore: generator and sampler brushed --- rtl/generator/src/generator.sv | 8 ++------ rtl/sampler/src/sampler.sv | 22 ---------------------- 2 files changed, 2 insertions(+), 28 deletions(-) diff --git a/rtl/generator/src/generator.sv b/rtl/generator/src/generator.sv index 902ad22..73fafe7 100644 --- a/rtl/generator/src/generator.sv +++ b/rtl/generator/src/generator.sv @@ -35,7 +35,8 @@ module generator start_d <= start; end - wire start_pulse = start & ~start_d; + wire start_pulse; + assign start_pulse = start & ~start_d; always @(posedge clk_in) begin @@ -53,11 +54,6 @@ module generator end else begin if (start) begin enable <= 1'b1; -// pulse_width_reg <= pulse_width; -// pulse_period_reg <= pulse_period; -// pulse_num_reg <= pulse_num; -// pulse_height_reg <= pulse_height; - cnt_pulse_num <= '0; cnt_period <= '0; end diff --git a/rtl/sampler/src/sampler.sv b/rtl/sampler/src/sampler.sv index 18a533c..23f0446 100644 --- a/rtl/sampler/src/sampler.sv +++ b/rtl/sampler/src/sampler.sv @@ -95,28 +95,6 @@ module sampler end endgenerate -// always @(posedge clk_in) begin -// if (rst) begin -// buffer <= '0; -// cnt <= '0; // -// buffer_ready <= 0; -// end -// else begin -// buffer_ready <= 0; -// if (!out_of_range_reg) begin -// buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted}; -// if (cnt == PACK_FACTOR-1) begin -// cnt <= 0; -// buffer_ready <= 1; -// buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted}; -// end -// else begin -// cnt <= cnt + 1; -// end -// end -// end -// end - assign m_axis_tdata = buffer; assign m_axis_tvalid = buffer_ready;