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rtl: rework out_axis_fifo

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Phil
2026-07-01 18:21:11 +03:00
parent 46333c3601
commit f0542845b0
1 changed files with 11 additions and 7 deletions
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18
rtl/accum/src/out_axis_fifo.sv
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@ -1,12 +1,12 @@
module out_axis_fifo #( module out_axis_fifo #(
parameter ACCUM_WIDTH = 32, parameter ACCUM_WIDTH = 32,
parameter WINDOW_SIZE = 65,
parameter PACKET_SIZE = 1024 parameter PACKET_SIZE = 1024
) ( ) (
input logic eth_clk_in, input logic eth_clk_in,
input logic acc_clk_in, input logic acc_clk_in,
input logic rst, input logic rst,
input logic [31:0] smp_num, input logic [31:0] smp_num,
input logic [31:0] window_size,
// AXI stream master for output, eth_clk_in domain // AXI stream master for output, eth_clk_in domain
output logic [7:0] m_axis_tdata, output logic [7:0] m_axis_tdata,
@ -85,6 +85,8 @@ module out_axis_fifo #(
reg [31:0] wr_cnt; // current BIT mem ptr reg [31:0] wr_cnt; // current BIT mem ptr
reg [31:0] wr_batch_tgt; // next 'target' that should be written from batch reg [31:0] wr_batch_tgt; // next 'target' that should be written from batch
reg [31:0] wr_total; // total BITS to be sent! reg [31:0] wr_total; // total BITS to be sent!
logic [31:0] window_size_reg;
wire [31:0] window_size_safe = (window_size == 32'd0) ? 32'd1 : window_size;
wire empty; wire empty;
@ -92,7 +94,7 @@ module out_axis_fifo #(
// NOTE: // NOTE:
// each written "acc_din" ACCUM_WIDTH word // each written "acc_din" ACCUM_WIDTH word
// is counted as WINDOWS_SIZE samples actually // is counted as window_size samples actually
// because hw division for counters is painful // because hw division for counters is painful
// so we just increased the counter sizes // so we just increased the counter sizes
@ -102,6 +104,7 @@ module out_axis_fifo #(
wr_cnt <= 32'b0; wr_cnt <= 32'b0;
wr_batch_tgt <= 32'b0; wr_batch_tgt <= 32'b0;
wr_total <= 32'b0; wr_total <= 32'b0;
window_size_reg <= 32'd1;
batch_req <= 0; batch_req <= 0;
finish <= 0; finish <= 0;
@ -115,6 +118,7 @@ module out_axis_fifo #(
wr_state <= WR_CHECK; wr_state <= WR_CHECK;
wr_total <= smp_num * ACCUM_WIDTH; wr_total <= smp_num * ACCUM_WIDTH;
wr_batch_tgt <= 32'b0; wr_batch_tgt <= 32'b0;
window_size_reg <= window_size_safe;
batch_req <= 0; batch_req <= 0;
finish <= 0; finish <= 0;
end end
@ -126,9 +130,9 @@ module out_axis_fifo #(
if ((wr_data_count < (FIFO_WDEPTH - (PACKET_SIZE / (ACCUM_WIDTH / 8)))) && ~wr_rst_busy) begin if ((wr_data_count < (FIFO_WDEPTH - (PACKET_SIZE / (ACCUM_WIDTH / 8)))) && ~wr_rst_busy) begin
batch_req <= 1; batch_req <= 1;
// should give us exactly PACKET_SIZE * 8 bits // should give us exactly PACKET_SIZE * 8 bits
// multiplied by WINDOW_SIZE, because we count // multiplied by window_size, because we count
// each given ACCUM_WIDTH word as WINDOWS_SIZE samples !!! // each given ACCUM_WIDTH word as window_size samples !!!
wr_batch_tgt <= wr_batch_tgt + (8 * WINDOW_SIZE * PACKET_SIZE); wr_batch_tgt <= wr_batch_tgt + (8 * window_size_reg * PACKET_SIZE);
wr_state <= WR_RUN; wr_state <= WR_RUN;
end else begin end else begin
batch_req <= 0; batch_req <= 0;
@ -150,8 +154,8 @@ module out_axis_fifo #(
if (din_valid) begin if (din_valid) begin
// data supplied // data supplied
// count as we got WINDOW_SIZE samples // count as we got window_size samples
wr_cnt <= wr_cnt + ACCUM_WIDTH * WINDOW_SIZE; wr_cnt <= wr_cnt + ACCUM_WIDTH * window_size_reg;
end end
end end