debugging testbench

designs/controller_dma_connective/tests/Makefile

@@ -11,6 +11,9 @@ VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
 VERILOG_SOURCES += $(RTL_DIR)/dma_reg_pkg.sv
 VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
 VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
 VERILOG_SOURCES += $(RTL_DIR)/controller.sv
 VERILOG_SOURCES += $(RTL_DIR)/dma_controller.sv
 VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_desc.sv

designs/controller_dma_connective/tests/test_controller_and_dma.py

@@ -57,11 +57,6 @@ class TB:
             dut.rst
         )
 
-        self.mem = AxiRam(
-            AxiBus.from_prefix( dut, "m_axi"),
-            dut.ctrl_clk,
-            dut.rst
-        )
 
         self.axis_source = AxiStreamSource(
             AxiStreamBus.from_prefix(dut, "s_axis_write_data"),