debugging testbench

2026-07-22 22:07:03 +03:00
parent 8648747380
commit ee83bcbb9e
2 changed files with 3 additions and 5 deletions
--- a/designs/controller_dma_connective/tests/Makefile
+++ b/designs/controller_dma_connective/tests/Makefile
@ -11,6 +11,9 @@ VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
 VERILOG_SOURCES += $(RTL_DIR)/dma_reg_pkg.sv
 VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
 VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
 VERILOG_SOURCES += $(RTL_DIR)/controller.sv
 VERILOG_SOURCES += $(RTL_DIR)/dma_controller.sv
 VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_desc.sv