baulin.fa/reflectometer_fpga_project
2
0
Fork 0
Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity

accumulator's changes for dma integration

Browse Source
This commit is contained in:
otroubi
2026-07-28 14:07:25 +03:00
parent 4acaea8d39
commit ea9a6ad1e6
4 changed files with 268 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files
rtl/accum/src/out_axis_fifo.sv
+18 -13
View File
@@ -1,15 +1,16 @@
module out_axis_fifo #(
parameter ACCUM_WIDTH = 32,
parameter WINDOW_SIZE = 65,
parameter RW_WIDTH = 32,
parameter PACKET_SIZE = 1024
) (
input logic eth_clk_in,
input logic dma_clk_in,
input logic acc_clk_in,
input logic rst,
input logic [31:0] smp_num,
input logic [31:0] window_size,
// AXI stream master for output, eth_clk_in domain
output logic [7:0] m_axis_tdata,
// AXI stream master for output, dma_clk_in domain
output logic [RW_WIDTH:0] m_axis_tdata,
output logic m_axis_tvalid,
input logic m_axis_tready,
output logic m_axis_tlast,
@@ -64,7 +65,7 @@ module out_axis_fifo #(
localparam int WDEPTH_BITS = $clog2(MIN_WR_WORDS);
localparam int FIFO_WDEPTH = 1 << WDEPTH_BITS;
localparam int FIFO_RDEPTH = FIFO_WDEPTH * ACCUM_WIDTH / 8;
localparam int FIFO_RDEPTH = FIFO_WDEPTH * ACCUM_WIDTH / RW_WIDTH;
localparam int RDEPTH_BITS = $clog2(FIFO_RDEPTH) + 1;
wire wr_unavail;
@@ -85,6 +86,8 @@ module out_axis_fifo #(
reg [31:0] wr_cnt; // current BIT mem ptr
reg [31:0] wr_batch_tgt; // next 'target' that should be written from batch
reg [31:0] wr_total; // total BITS to be sent!
logic [31:0] window_size_reg;
wire [31:0] window_size_safe = (window_size == 32'd0) ? 32'd1 : window_size;
wire empty;
@@ -92,7 +95,7 @@ module out_axis_fifo #(
// NOTE:
// each written "acc_din" ACCUM_WIDTH word
// is counted as WINDOWS_SIZE samples actually
// is counted as window_size samples actually
// because hw division for counters is painful
// so we just increased the counter sizes
@@ -102,6 +105,7 @@ module out_axis_fifo #(
wr_cnt <= 32'b0;
wr_batch_tgt <= 32'b0;
wr_total <= 32'b0;
window_size_reg <= 32'd1;
batch_req <= 0;
finish <= 0;
@@ -115,6 +119,7 @@ module out_axis_fifo #(
wr_state <= WR_CHECK;
wr_total <= smp_num * ACCUM_WIDTH;
wr_batch_tgt <= 32'b0;
window_size_reg <= window_size_safe;
batch_req <= 0;
finish <= 0;
end
@@ -126,9 +131,9 @@ module out_axis_fifo #(
if ((wr_data_count < (FIFO_WDEPTH - (PACKET_SIZE / (ACCUM_WIDTH / 8)))) && ~wr_rst_busy) begin
batch_req <= 1;
// should give us exactly PACKET_SIZE * 8 bits
// multiplied by WINDOW_SIZE, because we count
// each given ACCUM_WIDTH word as WINDOWS_SIZE samples !!!
wr_batch_tgt <= wr_batch_tgt + (8 * WINDOW_SIZE * PACKET_SIZE);
// multiplied by window_size, because we count
// each given ACCUM_WIDTH word as window_size samples !!!
wr_batch_tgt <= wr_batch_tgt + (8 * window_size_reg * PACKET_SIZE);
wr_state <= WR_RUN;
end else begin
batch_req <= 0;
@@ -150,8 +155,8 @@ module out_axis_fifo #(
if (din_valid) begin
// data supplied
// count as we got WINDOW_SIZE samples
wr_cnt <= wr_cnt + ACCUM_WIDTH * WINDOW_SIZE;
// count as we got window_size samples
wr_cnt <= wr_cnt + ACCUM_WIDTH * window_size_reg;
end
end
@@ -190,7 +195,7 @@ module out_axis_fifo #(
wire rd_valid;
wire [RDEPTH_BITS-1:0] rd_data_count;
always_ff @(posedge eth_clk_in) begin
always_ff @(posedge dma_clk_in) begin
if (rst_eth) begin
rd_state <= RD_IDLE;
send_req <= 1'b0;
@@ -307,7 +312,7 @@ module out_axis_fifo #(
.rd_clk(eth_clk_in), // 1-bit input: Read clock: Used for read operation. rd_clk must be a free running clock.
.rd_clk(dma_clk_in), // 1-bit input: Read clock: Used for read operation. rd_clk must be a free running clock.
.rd_en(rd_en), // 1-bit input: Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read
// from the FIFO. Must be held active-low when rd_rst_busy is active high.