diff --git a/rtl/generator/src/generator.sv b/rtl/generator/src/generator.sv
index 73fafe7..82d0457 100644
--- a/rtl/generator/src/generator.sv
+++ b/rtl/generator/src/generator.sv
@@ -13,77 +13,81 @@ module generator
     input [31:0]           pulse_period,
     input [DATA_WIDTH-1:0] pulse_height,
     input [15:0]           pulse_num,
+    input sample_done,
     
     output pulse,
-    output[DATA_WIDTH-1:0] pulse_height_out
+    output[DATA_WIDTH-1:0] pulse_height_out,
+    output logic sample_req
     
     );
     
-    logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
-    logic pulse_reg;
+  (* MARK_DEBUG="true" *)  logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
     
-    logic [31:0] pulse_width_reg, pulse_period_reg;
-    logic [15:0] pulse_num_reg;
+  (* MARK_DEBUG="true" *)  logic [31:0] pulse_width_reg, pulse_period_reg;
+  (* MARK_DEBUG="true" *)  logic [15:0] pulse_num_reg;
     
-    logic enable;
-    logic [15:0] cnt_pulse_num;
-    logic [31:0] cnt_period;
-    
-    logic start_d;
-
-    always @(posedge clk_in) begin
-        start_d <= start;
-    end
-
-    wire start_pulse;
-    assign start_pulse = start & ~start_d;
+  (* MARK_DEBUG="true" *)  logic enable;
+  (* MARK_DEBUG="true" *)  logic [15:0] cnt_pulse_num;
+  (* MARK_DEBUG="true" *)  logic [31:0] cnt_period;
 
     
     always @(posedge clk_in) begin
         if (rst) begin
-            pulse_reg <= '0;
             pulse_height_reg <= 0;
             pulse_height_out_reg <= '0;
-            
             pulse_width_reg <= '0;
             pulse_period_reg <= '0;
             pulse_num_reg <= '0;
             enable <= 0;
             cnt_pulse_num <= '0;
             cnt_period <= '0;
+            sample_req <= 0;
         end else begin
             if (start) begin
                 enable <= 1'b1;
                 cnt_pulse_num <= '0;
                 cnt_period <= '0;
-            end
-            if (enable) begin
-                pulse_reg <= 1;
+                
+                sample_req <= 1;
                 
                 pulse_width_reg <= pulse_width;
                 pulse_period_reg <= pulse_period;
                 pulse_num_reg <= pulse_num;
                 pulse_height_reg <= pulse_height;
-                
-                if (pulse_reg) begin
-                
-                if (cnt_period < pulse_width_reg) begin
-                    pulse_height_out_reg <= pulse_height_reg;
-                end else begin
+            end
+            if (enable) begin
+                if (!sample_req && (cnt_period == 0)) begin
                     pulse_height_out_reg <= '0;
-                end
-                if (cnt_period == pulse_period_reg - 1) begin
-                    cnt_period <= 0;
-                    if (cnt_pulse_num == pulse_num_reg - 1) begin
-                        enable <= 0;
-                        pulse_reg <= 0;
-                    end else begin
-                        cnt_pulse_num <= cnt_pulse_num + 1;
+                    if (sample_done) begin
+                        sample_req <= 1'b0;
+                    end
+                    
+                    if (!sample_done) begin
+                        if (cnt_pulse_num == pulse_num_reg - 1) begin
+                            enable <= 1'b0;
+                        end
+                        else begin
+                            cnt_pulse_num <= cnt_pulse_num + 1;
+                            sample_req <= 1'b1;
+                            cnt_period <= 1;
+                        end
                     end
-                end else begin
-                    cnt_period <= cnt_period + 1;
                 end
-                
+                 else begin
+                        
+                    if (cnt_period <= pulse_width_reg) begin
+                        pulse_height_out_reg <= pulse_height_reg;
+                    end else begin
+                        pulse_height_out_reg <= '0;
+                    end
+                    if (cnt_period == pulse_period_reg) begin
+                        cnt_period <= 0;
+                    end else begin
+                        cnt_period <= cnt_period + 1;
+                    end
+                    if (sample_req && sample_done) begin
+                        sample_req <= 0;
+                    end
                 end
             end
         end